公开(公告)号：US20250088246A1

公开(公告)日：2025-03-13

申请号：US18818316

申请日：2024-08-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Gilwon Lee ,  Md. Saifur Rahman ,  Eko Onggosanusi

IPC: H04B7/06 ,  H04B7/0456

Abstract: Apparatuses and methods for channel state information (CSI) reporting. A method performed by a user equipment (UE) includes receiving information about a channel state information (CSI) report. The information indicates Ng CSI reference signal (CSI-RS) resources, where Ng≥1. The method further includes, based on the information: measuring the Ng CSI-RS resources; identifying a number of groups of receive antenna ports, N, where N>1; and determining the CSI report associated with the Ng CSI-RS resources based on the number of groups of receive antenna ports. The method further includes transmitting the CSI report. The number of groups of receive antenna ports is according to a UE capability. The CSI report includes a rank indicator (RI) of ν layers, NPMI≥1 precoding matrix indicators (PMIs), and NCQI≥1 channel quality indicators (CQIs).

公开(公告)号：US20250087870A1

公开(公告)日：2025-03-13

申请号：US18957050

申请日：2024-11-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Youngkon LIM ,  Kihyuk Han ,  Hyoseok Na

IPC: H01Q1/24 ,  H01Q1/52 ,  H05K1/02

Abstract: An electronic device includes: a housing including a front surface and a rear surface; a display on the front surface of the housing; a shielding member being inside the housing; a printed circuit board on the shielding member, including: a first antenna area including a first pattern, a second antenna area including a second pattern, and a bending area, which is at least partially bent to interconnect the first antenna area and the second antenna area; and a rear surface plate on the rear surface of the housing to cover the printed circuit board, wherein the second pattern extends to outside of the first pattern and at least partially faces a portion of the first pattern.

公开(公告)号：US20250087743A1

公开(公告)日：2025-03-13

申请号：US18427499

申请日：2024-01-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyunjin KIM ,  Jungock PARK ,  Youngsin PARK ,  Joungwon PARK ,  Hyunpyo LEE ,  Jonghoon KA

IPC: H01M10/0562 ,  H01M4/02 ,  H01M4/583 ,  H01M4/66 ,  H01M10/26

Abstract: A sodium all-solid secondary battery including: a cathode; an anode; a sulfide-containing electrolyte between the cathode and the anode; an oxide-containing electrolyte between the sulfide-containing electrolyte and the anode; and a first bonding layer between the oxide-containing electrolyte and the sulfide-containing electrolyte, wherein the cathode includes a cathode current collector and a cathode active material layer, the anode includes an anode current collector and an anode active material layer, and the first bonding layer includes a metal capable of forming an alloy with sodium, a sodium ion-conductive material, or a combination thereof.

公开(公告)号：US20250087612A1

公开(公告)日：2025-03-13

申请号：US18626272

申请日：2024-04-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： JUNHYUN AN ,  UN-BYOUNG KANG ,  HYOJIN YUN ,  SEUNG HUN CHAE ,  JU-IL CHOI

IPC: H01L23/00

Abstract: The present disclosure relates to a conductive structure including: a conductive pad that includes a first seed layer having a first area and a second area surrounding the first area, and a first metal layer disposed on the first area of the first seed layer; and a conductive pillar disposed on the conductive pad, wherein a thickness of the conductive pad in an area vertically overlapping the first area of the first seed layer is thicker than a thickness of the conductive pad in an area vertically overlapping the second area of the first seed layer, a semiconductor chip including the conductive structure, and a manufacturing method of the conductive structure.

公开(公告)号：US20250087585A1

公开(公告)日：2025-03-13

申请号：US18731176

申请日：2024-05-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Youngjin Jung ,  Jaehwang Sim

IPC: H01L23/528 ,  H01L25/065 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40 ,  H10B80/00

Abstract: A semiconductor device includes a first word line having a first electrode portion and a first extension portion extending from the first electrode portion, a second word line having a second electrode portion disposed at a higher level than the first electrode portion and a second extension portion extending from the second electrode portion, a first vertical memory structure penetrating through the first and second electrode portions in a vertical direction, and a first interconnection structure electrically connected to the first extension portion. The first extension portion includes a first lower portion extending from the first electrode portion and a first plug portion extending upwardly from at least one side of the first lower portion and connected to the first interconnection structure. At least a portion of the first lower portion has a thickness greater than a thickness of the first electrode portion.

公开(公告)号：US20250087570A1

公开(公告)日：2025-03-13

申请号：US18626700

申请日：2024-04-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： HYUNSOO CHUNG ,  KWANG-SOO KIM ,  CHI WOO LEE

IPC: H01L23/498 ,  H01L21/56 ,  H01L23/29 ,  H01L23/31 ,  H01L25/065

Abstract: A semiconductor package includes a redistribution layer structure, a first sub-package positioned on the redistribution layer structure, a second sub-package positioned on the first sub-package, and a first encapsulant positioned on the first sub-package and encapsulating the second sub-package. The first sub-package includes a first semiconductor chip including a first chip through via and a dielectric through via electrically connected to the redistribution layer structure. The second sub-package includes a second semiconductor chip including a plurality of second chip through vias, each second chip through via electrically connected to one of the first chip through via and the dielectric through via, a third semiconductor chip positioned on the second semiconductor chip, and a fourth semiconductor chip positioned on the third semiconductor chip. Each of the second to fourth semiconductor chips is exposed at a side surface of the second sub-package and covered with the first encapsulant.

公开(公告)号：US20250087562A1

公开(公告)日：2025-03-13

申请号：US18816740

申请日：2024-08-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Narae Shin ,  Jeongkyu Ha ,  Woonbae Kim ,  Yechung Chung

IPC: H01L23/495 ,  H01L23/00 ,  H01L23/31

Abstract: A chip on film package includes a base film having a first surface and a second surface which are opposite to each other, at least one first conductive line disposed on the first surface and extending in a first direction, at least one second conductive line disposed on the second surface and extending in the first direction, a semiconductor chip disposed on the first surface and connected to the at least one first conductive line through a bump structure, a protective layer covering a part of the first surface and a part of the second surface, and a display panel disposed on the first surface and connected to the at least one first conductive line, wherein the at least one second conductive line is not disposed on the second surface between the semiconductor chip and the display panel.

公开(公告)号：US20250087465A1

公开(公告)日：2025-03-13

申请号：US18598037

申请日：2024-03-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyungsik Ko

IPC: H01J37/32 ,  H01L21/67 ,  H01L21/683

Abstract: Provided is a substrate processing apparatus including a chamber, an electrostatic chuck (ESC) in the chamber and configured to support a substrate, a shower head in the chamber and on the electrostatic chuck, and a ring assembly for a semiconductor process in the chamber and surrounding the electrostatic chuck, wherein the ring assembly for the semiconductor process includes a focus ring having a central axis extending in a first direction, an outer ring surrounding the focus ring, and a top ring on a top surface of the outer ring.

公开(公告)号：US20250087264A1

公开(公告)日：2025-03-13

申请号：US18958240

申请日：2024-11-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seongjin Kim ,  Jayang Yoon ,  Chiweon Yoon ,  Cheonan Lee ,  Kichang Jang

IPC: G11C11/4099 ,  G11C11/4074 ,  G11C11/408

Abstract: According to the present disclosure, a nonvolatile memory device may include an operational amplifier comparing a reference voltage with a voltage of a feedback node; a first feedback network circuit generating a first output voltage by dividing an input voltage in response to an output voltage of the operational amplifier, and transmitting a voltage corresponding to the first output voltage to the feedback node in response to a first feedback signal, a second feedback network circuit generating a second output voltage by dividing the input voltage in response to the output voltage of the operational amplifier, and transmitting a voltage corresponding to the second output voltage to the feedback node in response to a second feedback signal, and a third feedback network circuit generating a third output voltage by dividing the input voltage in response to the output voltage of the operational amplifier, and transmitting a voltage corresponding to the third output voltage to the feedback node in response to a third feedback signal.

公开(公告)号：US20250087018A1

公开(公告)日：2025-03-13

申请号：US18802774

申请日：2024-08-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Heejun YOU ,  Minsoo SHIN ,  Wonjung CHOI

IPC: G06V40/16 ,  G06V10/141 ,  G06V10/20 ,  H04N23/611 ,  H04N23/80

Abstract: An electronic device may comprise: an image sensor, an image pre-processor comprising circuitry, memory storing instructions, and at least one processor comprising processing circuitry. The instructions, when executed by at least one processor, individually and/or collectively, may cause the electronic device to: obtain raw data including biometric data using the image sensor. The instructions, when executed by at least one processor, individually and/or collectively, may cause the electronic device to store, in a first buffer, the raw data as first image data. The instructions, when executed by at least one processor, individually and/or collectively, may cause the electronic device to store, in a second buffer, second image data generated by applying a change operation to the raw data using the image pre-processor. The instructions, when executed by at least one processor, individually and/or collectively, may cause the electronic device to forward the first image data stored in the first buffer to a first application included in a secure area and apply a first algorithm for biometric authentication to the first image data. The instructions, when executed by at least one processor, individually and/or collectively, may cause the electronic device to forward the second image data stored in the second buffer to a second application included in a non-secure area and apply a second algorithm different from the first algorithm to the second image data. Other various embodiments are also available.