公开(公告)号：US20250087264A1

公开(公告)日：2025-03-13

申请号：US18958240

申请日：2024-11-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seongjin Kim ,  Jayang Yoon ,  Chiweon Yoon ,  Cheonan Lee ,  Kichang Jang

IPC: G11C11/4099 ,  G11C11/4074 ,  G11C11/408

Abstract: According to the present disclosure, a nonvolatile memory device may include an operational amplifier comparing a reference voltage with a voltage of a feedback node; a first feedback network circuit generating a first output voltage by dividing an input voltage in response to an output voltage of the operational amplifier, and transmitting a voltage corresponding to the first output voltage to the feedback node in response to a first feedback signal, a second feedback network circuit generating a second output voltage by dividing the input voltage in response to the output voltage of the operational amplifier, and transmitting a voltage corresponding to the second output voltage to the feedback node in response to a second feedback signal, and a third feedback network circuit generating a third output voltage by dividing the input voltage in response to the output voltage of the operational amplifier, and transmitting a voltage corresponding to the third output voltage to the feedback node in response to a third feedback signal.

公开(公告)号：US20240055380A1

公开(公告)日：2024-02-15

申请号：US18231838

申请日：2023-08-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Changbum KIM ,  Cheonan Lee ,  Sukkang Sung

IPC: H01L23/00 ,  H01L25/065 ,  H10B43/35 ,  H10B41/35

CPC classification number: H01L24/08 ,  H01L25/0657 ,  H10B43/35 ,  H10B41/35 ,  H10B80/00

Abstract: A semiconductor device includes: a first structure including a first substrate and a peripheral circuit disposed on the first substrate; and a second structure including a common source plate and a cell stack disposed on the common source plate and including a plurality of gate electrodes and channel structures, wherein the cell stack includes a plurality of cell blocks including a plurality of main blocks and at least one dummy block disposed at one side of the plurality of main blocks, wherein the common source plate includes a main common source line region and a dummy common source line region, wherein the main common source line region overlaps the plurality of main blocks, and the dummy common source line region is separated from the main common source line region and overlaps the at least one dummy block by being electrically isolated from the at least one dummy block.

公开(公告)号：US12190942B2

公开(公告)日：2025-01-07

申请号：US17863037

申请日：2022-07-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seongjin Kim ,  Jayang Yoon ,  Chiweon Yoon ,  Cheonan Lee ,  Kichang Jang

IPC: G11C11/4099 ,  G11C11/4074 ,  G11C11/408

Abstract: According to the present disclosure, a nonvolatile memory device may include an operational amplifier comparing a reference voltage with a voltage of a feedback node; a first feedback network circuit generating a first output voltage by dividing an input voltage in response to an output voltage of the operational amplifier, and transmitting a voltage corresponding to the first output voltage to the feedback node in response to a first feedback signal, a second feedback network circuit generating a second output voltage by dividing the input voltage in response to the output voltage of the operational amplifier, and transmitting a voltage corresponding to the second output voltage to the feedback node in response to a second feedback signal, and a third feedback network circuit generating a third output voltage by dividing the input voltage in response to the output voltage of the operational amplifier, and transmitting a voltage corresponding to the third output voltage to the feedback node in response to a third feedback signal.

公开(公告)号：US20230146885A1

公开(公告)日：2023-05-11

申请号：US17863037

申请日：2022-07-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seongjin Kim ,  Jayang Yoon ,  Chiweon Yoon ,  Cheonan Lee ,  Kichang Jang

IPC: G11C11/4099 ,  G11C11/4074 ,  G11C11/408

CPC classification number: G11C11/4099 ,  G11C11/4074 ,  G11C11/4085

Abstract: According to the present disclosure, a nonvolatile memory device may include an operational amplifier comparing a reference voltage with a voltage of a feedback node; a first feedback network circuit generating a first output voltage by dividing an input voltage in response to an output voltage of the operational amplifier, and transmitting a voltage corresponding to the first output voltage to the feedback node in response to a first feedback signal, a second feedback network circuit generating a second output voltage by dividing the input voltage in response to the output voltage of the operational amplifier, and transmitting a voltage corresponding to the second output voltage to the feedback node in response to a second feedback signal, and a third feedback network circuit generating a third output voltage by dividing the input voltage in response to the output voltage of the operational amplifier, and transmitting a voltage corresponding to the third output voltage to the feedback node in response to a third feedback signal.

公开(公告)号：US20240332431A1

公开(公告)日：2024-10-03

申请号：US18497363

申请日：2023-10-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jungmin Seo ,  Sukkang Sung ,  Cheonan Lee ,  Sangeun Lee ,  Chanho Lee

IPC: H01L29/861 ,  H01L27/02

CPC classification number: H01L29/8611 ,  H01L27/0248

Abstract: A semiconductor device according to an embodiment of the present inventive concept comprises: a first power supply pad configured to receive a first power supply voltage; a second power supply pad configured to receive a second power supply voltage, the second power supply voltage having a level lower than a level of the first power supply voltage; a signal pad configured to exchange a signal; and a first electrostatic discharge (ESD) diode comprising a first impurity region doped with impurities of a first conductivity type and connected to the first power supply pad, and a second impurity region doped with impurities of a second conductivity type different from the first conductivity type and connected to the signal pad, wherein a lower surface of at least one of the first impurity region and the second impurity region has an uneven structure.

公开(公告)号：US20240284683A1

公开(公告)日：2024-08-22

申请号：US18244429

申请日：2023-09-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jungmin Seo ,  Manho Lee ,  Sukkang Sung ,  Cheonan Lee

IPC: H10B80/00 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18

CPC classification number: H10B80/00 ,  H01L25/0652 ,  H01L25/18 ,  H01L25/50 ,  H01L2225/06506 ,  H01L2225/06537 ,  H01L2225/06562 ,  H01L2225/06582

Abstract: A nonvolatile memory package includes first nonvolatile memory devices configured to be stacked, second nonvolatile memory devices configured to be stacked, and an interface chip connected to an external device through a bonding channel, connected to one of the first nonvolatile memory devices through a first bonding channel, and connected to one of the second nonvolatile memory devices through a second bonding channel, wherein the interface chip includes input/output pads connected to the bonding channel, first input/output pads connected to the first bonding channel, and second input/output pads connected to the second bonding channel, and wherein, for cross-channel shielding, the first input/output pads and the second input/output pads are alternately arranged for each channel.

公开(公告)号：US20230307068A1

公开(公告)日：2023-09-28

申请号：US18184842

申请日：2023-03-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yoonjae LEE ,  Byungjoon Yoo ,  Chiweon Yoon ,  Cheonan Lee

IPC: G11C16/30 ,  H02M3/07 ,  G11C16/32

CPC classification number: G11C16/30 ,  H02M3/07 ,  G11C16/32

Abstract: A memory device includes a memory cell array region electrically connected to a plurality of word lines and a plurality of bit lines and the memory cell array including a plurality of memory cells, and a peripheral circuit region under the memory cell array region, wherein the memory cell array region and the peripheral circuit region are electrically connected by through vias, the peripheral circuit region includes a voltage generator configured to generate an operating voltage to apply to the word lines, the voltage generator includes a pumping capacitor unit configured to charge and pump a voltage based on a clock signal, and a signal controller configured to control the clock signal and a current flowing through the pumping capacitor unit, the signal controller includes a clock driver configured to apply a clock signal to the pumping capacitor, and the signal controller is adjacent to the through vias.

公开(公告)号：US11430515B2

公开(公告)日：2022-08-30

申请号：US17036004

申请日：2020-09-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyunghwan Lee ,  Yongseok Kim ,  Cheonan Lee ,  Satoru Yamada ,  Junhee Lim

IPC: G11C13/00 ,  H01L27/24

Abstract: A resistive memory device includes a memory cell array, control logic, a voltage generator, and a read-out circuit. The memory cell array includes memory cells connected to bit lines. Each memory cell includes a variable resistance element to store data. The control logic receives a read command and generates a voltage control signal for generating a plurality of read voltages based on the read command. The voltage generator sequentially applies the read voltages to the bit lines based on the voltage control signal. The read-out circuit is connected to the bit lines. The control logic determines values of data stored in the memory cells by controlling the read-out circuit to sequentially compare values of currents sequentially output from the memory cells in response to the plurality of read voltages with a reference current.