公开(公告)号：US11495686B2

公开(公告)日：2022-11-08

申请号：US17147468

申请日：2021-01-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chi-Hsuan Tang ,  Chung-Ting Huang ,  Bo-Shiun Chen ,  Chun-Jen Chen ,  Yu-Shu Lin

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L21/02

Abstract: A method for fabricating a semiconductor device includes the steps of first forming a gate structure on a substrate, forming a first spacer adjacent to the gate structure, forming a second spacer adjacent to the first spacer, forming an epitaxial layer adjacent to the second spacer, forming a second cap layer on the epitaxial layer, and then forming a first cap layer on the second cap layer. Preferably, a top surface of the first cap layer includes a V-shape and the first cap layer and the second cap layer are made of different materials.

公开(公告)号：US11495681B2

公开(公告)日：2022-11-08

申请号：US17067775

申请日：2020-10-12

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chang-Po Hsiung ,  Ching-Chung Yang ,  Shan-Shi Huang ,  Shin-Hung Li ,  Nien-Chung Li ,  Wen-Fang Lee ,  Chiu-Te Lee ,  Chih-Kai Hsu ,  Chun-Ya Chiu ,  Chin-Hung Chen ,  Chia-Jung Hsu ,  Ssu-I Fu ,  Yu-Hsiang Lin

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/423 ,  H01L21/02 ,  H01L29/66 ,  H01L21/311 ,  H01L21/28

Abstract: A semiconductor device includes a semiconductor substrate, a recess, a first gate oxide layer, and a gate structure. The semiconductor substrate includes a first region and a second region adjacent to the first region. The recess is disposed in the first region of the semiconductor substrate, and an edge of the recess is located at an interface between the first region and the second region. At least a part of the first gate oxide layer is disposed in the recess. The first gate oxide layer includes a hump portion disposed adjacent to the edge of the recess, and a height of the hump portion is less than a depth of the recess. The gate structure is disposed on the first region and the second region of the semiconductor substrate, and the gate structure overlaps the hump portion of the first gate oxide layer in a vertical direction.

公开(公告)号：US20220352459A1

公开(公告)日：2022-11-03

申请号：US17867702

申请日：2022-07-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hui-Lin Wang ,  Chia-Chang Hsu ,  Chen-Yi Weng ,  Chin-Yang Hsieh ,  Jing-Yin Jhang

IPC: H01L43/02 ,  H01L43/12 ,  H01L27/22 ,  H01F41/34 ,  H01F10/32 ,  G11C11/16

Abstract: A semiconductor device includes a substrate comprising a MTJ region and a logic region, a magnetic tunneling junction (MTJ) on the MTJ region, and a contact plug on the logic region. Preferably, the MTJ includes a bottom electrode layer having a gradient concentration, a free layer on the bottom electrode layer, and a top electrode layer on the free layer.

公开(公告)号：US20220352195A1

公开(公告)日：2022-11-03

申请号：US17864435

申请日：2022-07-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Liang Yi ,  ZHIGUO LI ,  CHI REN

IPC: H01L27/11578 ,  H01L29/66 ,  H01L27/11551 ,  H01L29/78

Abstract: A silicon-oxide-nitride-oxide-silicon (SONOS) memory cell for FinFET includes a fin, a control gate and a selective metal gate. The fin is on a top surface of a substrate, wherein the fin has two sidewalls and a top surface, and the fin includes a memory region and a logic region. The control gate is disposed over the fin of the memory region and covers the two sidewalls and the top surface of the fin, wherein the control gate includes a charge trapping layer and a control electrode, wherein the charge trapping layer is sandwiched by the fin and the control electrode. The selective metal gate is disposed over the fin adjacent to the control gate and covers the two sidewalls and the top surface of the fin. The present invention also provides a method of forming said silicon-oxide-nitride-oxide-silicon (SONOS) memory cell.

公开(公告)号：US11488949B1

公开(公告)日：2022-11-01

申请号：US17340119

申请日：2021-06-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuo-Liang Yeh ,  Jinn-Horng Lai ,  Ching-Wen Hung ,  Chien-Tung Yue ,  Chun-Li Lin

IPC: G06F17/00 ,  H01L27/02 ,  G01R35/00

Abstract: The present invention provides a method of generating dummy patterns and calibration kits, including steps of generating devices-under-test (DUTs) using a point of said chip window layer as reference point in a unit cell, generating calibration kits corresponding to the DUTs using the point as reference point in corresponding unit cells, generating DUT dummy patterns for each DUTs individually in the unit cell, copying the DUT dummy patterns in the unit cell to the corresponding calibration kits in the corresponding unit cells using the point as reference point, and merging all of the unit cell and corresponding unit cells into a final chip layout.

公开(公告)号：US11488837B2

公开(公告)日：2022-11-01

申请号：US17030158

申请日：2020-09-23

Applicant: United Microelectronics Corp.

Inventor： Chia-Jung Hsu ,  Chun Yu Chen ,  Chin-Hung Chen ,  Chun-Ya Chiu ,  Chih-Kai Hsu ,  Ssu-I Fu ,  Yu-Hsiang Lin

IPC: H01L21/324 ,  H01L21/28 ,  H01L29/66 ,  H01L29/06 ,  H01L21/02 ,  H01L21/311

Abstract: A method for fabricating a high-voltage (HV) transistor is provided. The method includes providing a substrate, having a first isolation structure and a second isolation structure in the substrate and a recess in the substrate between the first and second isolation structures. Further, a hydrogen annealing process is performed over the recess. A sacrificial dielectric layer is formed on the recess. The sacrificial dielectric layer is removed, wherein a portion of the first and second isolation structures is also removed. A gate oxide layer is formed in the recess between the first and second isolation structures after the hydrogen annealing process.

公开(公告)号：US11488829B1

公开(公告)日：2022-11-01

申请号：US17337457

申请日：2021-06-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuan-Ying Lai ,  Hsin-Yu Hsieh ,  Chang-Mao Wang ,  Chung-Yi Chiu

IPC: H01L21/28 ,  H01L21/3213 ,  H01L29/49

Abstract: A method of forming a semiconductor device is disclosed. A substrate having a first device region and a second device region is provided. A metal nitride barrier layer is formed to cover the first device region and the second device region. A titanium layer is deposited on the metal nitride barrier layer. The titanium layer is selectively removed from the second device region, thereby exposing the metal nitride barrier layer in the second device region. The titanium layer in the first device region is transformed into a titanium nitride layer. The titanium nitride layer is a work function layer on the first device region.

公开(公告)号：US20220344321A1

公开(公告)日：2022-10-27

申请号：US17348784

申请日：2021-06-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kun-Yuan Wu ,  Wei-Jen Wang ,  Chien-Fu Chen ,  Chen-Hsien Hsu ,  Chien-Hung Chen ,  Chun-Hsien Lin

IPC: H01L27/02

Abstract: An integrated circuit layout includes a first standard cell and a second standard cell. The first standard cell includes first gate lines arranged along a first direction and extending along a second direction. The second standard cell abuts to one side of the first standard cell along the second direction and includes second gate lines arranged along the first direction and extending along the second direction. A first gate line width of the first gate lines and a second gate line width of the second gate lines are different. A first cell width of the first standard cell and a second cell width of the second standard cell are integral multiples of a default gate line pitch of the first gate lines and the second gate lines. At least some of the second gate lines and at least some of the first gate lines are aligned along the second direction.

公开(公告)号：US11482666B2

公开(公告)日：2022-10-25

申请号：US17023382

申请日：2020-09-17

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hsin-Jung Liu ,  Chau-Chung Hou ,  Ang Chan ,  Kun-Ju Li ,  Wen-Chin Lin

IPC: H01L43/12 ,  H01L27/22 ,  H01L43/08 ,  H01L43/02 ,  H01L43/10

Abstract: A semiconductor substrate is provided. The semiconductor substrate has thereon a first dielectric layer, at least one conductive pattern disposed in the first dielectric layer, and a second dielectric layer covering the first dielectric layer and the at least one conductive pattern. A via opening is formed in the second dielectric layer. The via opening exposes a portion of the at least one conductive pattern. A polish stop layer is conformally deposited on the second dielectric layer and within the via opening. A barrier layer is conformally deposited on the polish stop layer. A tungsten layer is conformally deposited on the barrier layer. The tungsten layer and the barrier layer are polished until the polish stop layer on the second dielectric layer is exposed, thereby forming a via plug in the via opening. A bottom electrode layer is conformally deposited on the second dielectric layer and the via plug.

公开(公告)号：US20220336606A1

公开(公告)日：2022-10-20

申请号：US17853954

申请日：2022-06-30

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Hao Pan ,  Chi-Cheng Huang ,  Kuo-Lung Li ,  Szu-Ping Wang ,  Po-Hsuan Chen ,  Chao-Sheng Cheng

IPC: H01L29/423 ,  H01L29/792 ,  H01L21/28 ,  H01L29/66

Abstract: A memory cell includes a substrate. A first STI and a second STI are embedded within the substrate. The first STI and the second STI extend along a first direction. An active region is disposed on the substrate and between the first STI and the second STI. A control gate is disposed on the substrate and extends along a second direction. The first direction is different from the second direction. A tunneling region is disposed in the active region overlapping the active region. A first trench is embedded within the tunneling region. Two second trenches are respectively embedded within the first STI and the second STI. The control gate fills in the first trench and the second trenches. An electron trapping stack is disposed between the tunneling region and the control gate.