公开(公告)号：US6104058A

公开(公告)日：2000-08-15

申请号：US898155

申请日：1997-07-22

Applicant: Claudio Brambilla ,  Giancarlo Ginami ,  Stefano Daffra ,  Andrea Ravaglia ,  Manlio Sergio Cereda

Inventor： Claudio Brambilla ,  Giancarlo Ginami ,  Stefano Daffra ,  Andrea Ravaglia ,  Manlio Sergio Cereda

IPC: H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC classification number: H01L27/11521 ,  H01L27/115

Abstract: A method for improving the intermediate dielectric profile, particularly for non-volatile memories constituted by a plurality of cells, including the following steps: forming field oxide regions and drain active area regions on a substrate; forming word lines on the field oxide regions; depositing oxide to form oxide wings that are adjacent to the word lines; opening, by masking, source regions and the drain active area regions, keeping the field oxide regions that separate one memory cell from the other, inside the memory, covered with resist; and removing field oxide in the source regions and removing oxide wings from both sides of the word lines.

Abstract translation: 一种用于改善中间介质轮廓的方法，特别是用于由多个单元构成的非易失性存储器，包括以下步骤：在衬底上形成场氧化物区域和漏极活性区域区域; 在场氧化物区域上形成字线; 沉积氧化物以形成与字线相邻的氧化物翼; 通过掩蔽来源区域和漏极有源区域区域，保持在抗蚀剂覆盖的存储器内部的一个存储单元与另一个存储单元分离的场氧化物区域; 并且去除源区域中的场氧化物并从字线的两侧去除氧化物翼。

公开(公告)号：US06097057A

公开(公告)日：2000-08-01

申请号：US996921

申请日：1997-12-23

Applicant: Giovanna Dalla Libera ,  Bruno Vajana ,  Roberta Bottini ,  Carlo Cremonesi

Inventor： Giovanna Dalla Libera ,  Bruno Vajana ,  Roberta Bottini ,  Carlo Cremonesi

IPC: H01L21/8247 ,  H01L29/788

CPC classification number: H01L27/11521 ,  H01L27/11524

Abstract: A memory cell for devices of the EEPROM type, formed in a portion of a semiconductor material substrate having a first conductivity type. The memory cell includes source and drain regions having a second conductivity type and extending at the sides of a gate oxide region which includes a thin tunnel oxide region. The memory cell also includes a region of electric continuity having the second conductivity type, being formed laterally and beneath the thin tunnel oxide region, and partly overlapping the drain region, and a channel region extending between the region of electric continuity and the source region. The memory cell further includes an implanted region having the first conductivity type and being formed laterally and beneath the gate oxide region and incorporating the channel region.

公开(公告)号：US6080626A

公开(公告)日：2000-06-27

申请号：US996923

申请日：1997-12-23

Applicant: Bruno Vajana ,  Carlo Cremonesi ,  Roberta Bottini ,  Giovanna Dalla Libera

Inventor： Bruno Vajana ,  Carlo Cremonesi ,  Roberta Bottini ,  Giovanna Dalla Libera

IPC: H01L21/8247

CPC classification number: H01L27/11521 ,  H01L27/11524

Abstract: A memory cell of the EEPROM type formed on a semiconductor material substrate having a first conductivity type includes a drain region having a second conductivity type and extending at one side of a gate oxide region which includes a thin tunnel oxide region. The memory cell also includes a region of electric continuity having the second conductivity type, being formed laterally and beneath the thin tunnel oxide region, and partly overlapping the drain region. The region of electric continuity is produced by implantation at a predetermined angle of inclination.

Abstract translation: 形成在具有第一导电类型的半导体材料基板上的EEPROM型存储单元包括具有第二导电类型的漏极区域，并且在包括薄隧道氧化物区域的栅极氧化物区域的一侧延伸。 存储单元还包括具有第二导电类型的电连续性区域，横向形成在薄隧道氧化物区域下方，并且部分地与漏极区域重叠。 通过以预定的倾斜角度的注入产生电连续性的区域。

公开(公告)号：US6064087A

公开(公告)日：2000-05-16

申请号：US739466

申请日：1996-10-29

Applicant: Angelo Magri' ,  Ferruccio Frisina ,  Giuseppe Ferla

Inventor： Angelo Magri' ,  Ferruccio Frisina ,  Giuseppe Ferla

IPC: H01L29/74 ,  H01L21/331 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/749 ,  H01L29/78 ,  H01L29/76 ,  H01L29/94

CPC classification number: H01L29/66333 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/7802 ,  H01L29/0847

Abstract: A MOS technology power device comprises a semiconductor material layer of a first conductivity type, a conductive insulated gate layer covering the semiconductor material layer, and a plurality of elementary functional units. The conductive insulated gate layer includes a first insulating material layer placed above the semiconductor material layer, a conductive material layer placed above the first insulating material layer, and a second insulating material layer placed above the conductive material layer. Each elementary functional unit includes an elongated body region of a second conductivity type formed in the semiconductor material layer. Each elementary functional unit further includes an elongated window in the insulated gate layer extending above the elongated body region. Each elongated body region includes a source region doped with dopants of the first conductivity type, intercalated with a portion of the elongated body region wherein no dopant of the first conductivity type are provided. The MOS technology power device further includes a plurality of insulating material sidewall spacers disposed above the semiconductor material layer along elongated edges of each elongated window to seal the edges of each elongated window in the insulated gate layer from a source metal layer disposed over the insulated gate layer and the semiconductor material layer. The source metal layer contacts each body region and each source region through each elongated window along the length of the elongated body region.

公开(公告)号：US6057191A

公开(公告)日：2000-05-02

申请号：US877335

申请日：1997-06-17

Applicant: Maurizio Moroni

Inventor： Maurizio Moroni

IPC: H01L21/265 ,  H01L21/285 ,  H01L21/336

CPC classification number: H01L21/28512 ,  H01L21/26586

Abstract: A process for the manufacturing of integrated circuits provides for forming contacts between a conductive material layer and first doped regions of a semiconductor substrate in a self-aligned manner to edges of an insulating material layer which defines active areas of the integrated circuit wherein the doped regions are formed, and second doped regions of the same conductivity type as the first doped regions under the first doped regions, the second doped regions extending partially under the edges of the insulating material layer to prevent short-circuits between the conductive material layer and the semiconductor substrate. The second doped regions are formed by means of implantation of dopants along directions slanted with respect to an orthogonal direction to a surface of the semiconductor substrate at angles and with an energy sufficiently high to make the dopants penetrate in the semiconductor material deeper than the first doped regions and under the edges of the insulating material layer.

Abstract translation: 用于制造集成电路的工艺提供了以自对准的方式在导电材料层和半导体衬底的第一掺杂区之间形成接触，该绝缘材料层定义了集成电路的有源区，其中掺杂区 以及与第一掺杂区域下方的第一掺杂区域相同的导电类型的第二掺杂区域，第二掺杂区域部分地延伸在绝缘材料层的边缘下方，以防止导电材料层和半导体之间的短路 基质。 第二掺杂区域通过沿着相对于半导体衬底的表面的正交方向以角度倾斜并且以足够高的能量倾斜的方式形成掺杂剂，以使掺杂剂在半导体材料中比第一掺杂 区域和绝缘材料层的边缘下方。

公开(公告)号：US6043532A

公开(公告)日：2000-03-28

申请号：US965840

申请日：1997-11-07

Applicant: Riccardo Depetro ,  Michele Palmieri

Inventor： Riccardo Depetro ,  Michele Palmieri

IPC: H01L29/06 ,  H01L29/10 ,  H01L29/423 ,  H01L29/78 ,  H01L29/76

CPC classification number: H01L29/7816 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/7802 ,  H01L29/4238

Abstract: The DMOS transistor includes an n drain region, a p body region which forms, with the drain region, a junction having at least one edge portion with a small radius of curvature, an n+ source region which delimits a channel in the body region, p+ body contact regions, a gate electrode, a source and body electrode, and a drain electrode. To prevent the "snap-back" phenomenon when the junction is reverse biased with the source, body and gate electrodes short-circuited, a p+ region is associated with each of the edge portions having a small radius of curvature and is arranged so as to be closer to the associated edge portion than any part of the source region.

Abstract translation: DMOS晶体管包括n个漏极区域，其与漏极区域形成具有至少一个具有小曲率半径的边缘部分的接合部的p体区域，限定身体区域中的通道的n +源极区域，p +体 接触区域，栅极电极，源极和主体电极以及漏极电极。 为了防止当源极，主体和栅极短路时结在反向偏置时的“回扣”现象，p +区与每个具有小曲率半径的边缘部分相关联，并且布置成 比源区域的任何部分更靠近相关联的边缘部分。

公开(公告)号：US6020623A

公开(公告)日：2000-02-01

申请号：US984910

申请日：1997-12-04

Applicant: Giorgio Chiozzi

Inventor： Giorgio Chiozzi

IPC: H01L20060101 ,  H01L27/07 ,  H01L29/08 ,  H01L29/735 ,  H01L29/866 ,  H01L27/082 ,  H01L27/102 ,  H01L31/11 ,  H01L29/90

CPC classification number: H01L29/866 ,  H01L27/0783 ,  H01L29/0808 ,  H01L29/735

Abstract: An integrated structure is made in a chip of semiconductor material inside an insulated N type region extending from a surface of the chip. The structure comprises a Zener diode formed by a P type first region extending from the surface inside the insulated region and by a second region of type N extending from the surface inside the first region. These regions form between themselves a buried junction, in which the structure further includes a lateral bipolar transistor having an emitter region provided by the first region.

Abstract translation: 在从芯片的表面延伸的绝缘N型区域内的半导体材料的芯片中形成一体的结构。 该结构包括由绝缘区域内的表面延伸的P型第一区域和从第一区域内的表面延伸的N型第二区域形成的齐纳二极管。 这些区域在它们之间形成掩埋结，其中结构还包括具有由第一区域提供的发射极区域的横向双极晶体管。

公开(公告)号：USRE36508E

公开(公告)日：2000-01-18

申请号：US932000

申请日：1997-09-17

Applicant: Silvano Gornati ,  Giorgio Betti ,  Fabrizio Sacchi ,  Gianfranco Vai ,  Maurizio Zuffada

Inventor： Silvano Gornati ,  Giorgio Betti ,  Fabrizio Sacchi ,  Gianfranco Vai ,  Maurizio Zuffada

IPC: H04N5/04 ,  H04N5/46 ,  H04N17/04 ,  H04N5/08 ,  H04N7/01

CPC classification number: H04N17/04 ,  H04N5/04 ,  H04N5/46

Abstract: A method of automatically measuring the horizontal scan frequency of a composite synchronism signal, comprising horizontal synchronization impulses at line frequency, consists of first performing a count of a number of impulses having a repeat frequency higher than said line frequency, as intervening between two successive impulses at line frequency.The count value, corresponding to said number of impulses, is stored to obtain the line frequency of the signal, and thereafter, a series of down counts is effected, as initiated at predetermined times, until a change of frequency of the signal is detected.

Abstract translation: 一种自动测量复合同步信号的水平扫描频率的方法，包括在线频率处的水平同步脉冲，包括首先执行具有高于所述线频率的重复频率的多个脉冲的计数，作为介于两个连续脉冲之间 在线频率。 存储对应于所述脉冲数的计数值以获得信号的线路频率，然后在预定时间开始进行一系列递减计数，直到检测到信号的频率变化。

公开(公告)号：US06016073A

公开(公告)日：2000-01-18

申请号：US965068

申请日：1997-11-05

Applicant: Andrea Ghilardelli ,  Jacopo Mulatti ,  Maurizio Branchetti

Inventor： Andrea Ghilardelli ,  Jacopo Mulatti ,  Maurizio Branchetti

IPC: H01L21/8247 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/788 ,  H01L29/792 ,  H02M3/07 ,  G06F1/10

CPC classification number: H02M3/073

Abstract: A charge pump includes a plurality of stages connected in series between a reference potential and an output terminal of the charge pump. The plurality of stages includes a first group of stages, proximate to the reference potential, and a second group of stages proximate to the output terminal of the charge pump. Each stage of the first group includes a pass-transistor with first and second terminals respectively connected to an input and an output of the stage, and a first capacitor with a first plate connected to the output of the stage and a second plate driven by a digital signal switching between the reference voltage and a positive voltage. Each stage of the second group includes a junction diode having a first electrode connected to an input of the stage and a second electrode connected to an output of the stage, and a second capacitor having a first plate connected to the output of the stage and a second plate driven by a digital signal switching between the reference voltage and the voltage supply.

Abstract translation: 电荷泵包括串联连接在电荷泵的参考电位和输出端之间的多个级。 多个级包括靠近参考电位的第一组级，以及靠近电荷泵输出端的第二组级。 第一组的每个级包括通过晶体管，其中第一和第二端子分别连接到级的输入端和输出端，第一电容器具有连接到级的输出端的第一板和由第一板驱动的第二板 数字信号在参考电压和正电压之间切换。 第二组的每一级包括结二极管，其具有连接到该级的输入的第一电极和连接到该级的输出的第二电极，以及一第二电容器，该第二电容器具有连接到该级的输出的第一电极和 第二板由参考电压和电压源之间的数字信号切换驱动。

公开(公告)号：US6004847A

公开(公告)日：1999-12-21

申请号：US667097

申请日：1996-06-20

Applicant: Cesare Clementi ,  Gabriella Ghidini ,  Carlo Riva

Inventor： Cesare Clementi ,  Gabriella Ghidini ,  Carlo Riva

IPC: H01L21/8247 ,  H01L27/105

CPC classification number: H01L27/11526 ,  H01L27/105 ,  H01L27/11546

Abstract: A process for forming an integrated circuit includes at least one matrix of non-volatile memory cells having an intermediate dielectric multilayer including at least a lower dielectric material layer and an upper silicon oxide layer. The integrated circuit includes at least one transistor simultaneously formed in zones peripheral to the matrix and having a gate dielectric of a first thickness. After formation of the floating gate with a gate oxide layer and a polycrystalline silicon layer and the formation of the lower dielectric material layer, the process includes removal of said layers from the peripheral zones of the matrix; deposition of said upper silicon oxide layer over the memory cells, and over the substrate in the areas of the peripheral transistors; and formation of a first silicon oxide layer at least in the areas of the peripheral transistors. A second transistor type can be formed having a gate dielectric of a second thickness, thinner than said first thickness, in successive steps.

Abstract translation: 一种用于形成集成电路的工艺包括至少一个非易失性存储单元阵列，其具有至少包含下介电材料层和上氧化硅层的中间介电层。 该集成电路包括至少一个晶体管，同时形成在基体周边的区域中，并且具有第一厚度的栅极电介质。 在形成具有栅极氧化物层和多晶硅层的浮置栅极和形成下部电介质材料层之后，该工艺包括从基体的周边区域去除所述层; 所述上氧化硅层沉积在所述存储单元上，并在所述外围晶体管的区域中的衬底上; 以及至少在周边晶体管的区域中形成第一氧化硅层。 第二晶体管类型可以在连续的步骤中形成具有比所述第一厚度更薄的第二厚度的栅极电介质。