公开(公告)号：US11539908B2

公开(公告)日：2022-12-27

申请号：US15721125

申请日：2017-09-29

Applicant: Advanced Micro Devices, Inc.

Inventor： Ngoc Vinh Vu ,  Adam William Lynch ,  Darren Rae Di Cera ,  Stephen Mark Ryan

IPC: H04N5/40 ,  H04N19/36 ,  H04N19/187 ,  H04N19/66 ,  H04N19/30 ,  H04L1/00 ,  H04N19/29 ,  H04N19/67 ,  H04N21/426 ,  H04N5/46 ,  H04N1/00 ,  H04N21/63 ,  H04N7/24

Abstract: Systems, apparatuses, and methods for utilizing different modulation coding schemes (MCSs) for different components of a video stream are disclosed. A system includes a transmitter sending a video stream over a wireless link to a receiver. The transmitter splits the video stream into low, medium, and high quality components, and then the transmitter modulates the different components using different MCS's. For example, the transmitter modulates the low quality component using a lower, robust MCS level to increase the likelihood that this component is received. Also, the medium quality component is modulated using a medium MCS level and the high frequency component is modulated using a higher MCS level. If only the low quality component is received by the receiver, then the receiver reconstructs and displays a low quality video frame from this component, which avoids a glitch in the display of the video stream.

公开(公告)号：US11537319B2

公开(公告)日：2022-12-27

申请号：US16710563

申请日：2019-12-11

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Alexander Fuad Ashkar ,  James R. Klobcar ,  Harry J. Wise

IPC: G06F3/06 ,  G11C15/04

Abstract: A processing system includes a content addressable memory (CAM) in an input/output path to selectively modify register writes on a per-pipeline basis. The CAM compares an address of a register write to an address field of each entry of the CAM. If a match is found, the CAM modifies the register write data as defined by a function for the matching entry of the CAM. In some embodiments, each entry of the CAM includes a data mask defining subfields of the register write data, wherein each subfield includes subfield data including one or more bits.

公开(公告)号：US11527270B2

公开(公告)日：2022-12-13

申请号：US17359253

申请日：2021-06-25

Applicant: Advanced Micro Devices, Inc.

Inventor： John J. Wuu ,  Russell J. Schreiber

IPC: G11C7/00 ,  G11C7/10 ,  H03K19/173 ,  G11C7/12

Abstract: A static random access memory (SRAM) includes fast SRAM bit cells and fast multiplexer circuits that are formed in a first row of fast cells in a hybrid standard cell architecture. Slow SRAM bit cells and slow multiplexer circuits are formed in a second row of slow cells. The slow multiplexer circuits provide a column output for the fast SRAM bit cells and the fast multiplexer circuits provide a column output for the slow SRAM bit cells. Thus, one SRAM column has fast bit cells and slow multiplexer stages while the adjacent SRAM column has slow bit cells and fast multiplexer stages to thereby provide an improved performance balance when reading the SRAM.

公开(公告)号：US11521342B2

公开(公告)日：2022-12-06

申请号：US17230140

申请日：2021-04-14

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Maxim V. Kazakov ,  Mark Fowler

IPC: G06T15/04 ,  G06T15/00

Abstract: A processor receives a request to access one or more levels of a partially resident texture (PRT) resource. The levels represent a texture at different levels of detail (LOD) and the request includes normalized coordinates indicating a location in the texture. The processor accesses a texture descriptor that includes dimensions of a first level of the levels and one or more offsets between a reference level and one or more second levels that are associated with one or more residency maps that indicate texels that are resident in the PRT resource. The processor translates the normalized coordinates to texel coordinates in the one or more residency maps based on the offset and accesses, in response to the request, the one or more residency maps based on the texel coordinates to determine whether texture data indicated by the normalized coordinates is resident in the PRT resource.

公开(公告)号：US20220382550A1

公开(公告)日：2022-12-01

申请号：US17886855

申请日：2022-08-12

Applicant: Advanced Micro Devices, Inc.

Inventor： Andrew G. Kegel

IPC: G06F9/30 ,  G06F9/48 ,  G06F30/34

Abstract: Systems, apparatuses, and methods for implementing as part of a processor pipeline a reprogrammable execution unit capable of executing specialized instructions are disclosed. A processor includes one or more reprogrammable execution units which can be programmed to execute different types of customized instructions. When the processor loads a program for execution, the processor loads a bitfile associated with the program. The processor programs a reprogrammable execution unit with the bitfile so that the reprogrammable execution unit is capable of executing specialized instructions associated with the program. During execution, a dispatch unit dispatches the specialized instructions to the reprogrammable execution unit for execution. The results of other instructions, such as integer and floating point instructions, are available immediately to instructions executing on the reprogrammable execution unit since the reprogrammable execution unit shares the processor registers with the integer and floating point execution units.

公开(公告)号：US11513802B2

公开(公告)日：2022-11-29

申请号：US17033883

申请日：2020-09-27

Applicant: Advanced Micro Devices, Inc.

Inventor： Michael W. Boyer ,  John Kalamatianos ,  Pritam Majumder

IPC: G06F9/38 ,  G06F9/22

Abstract: An electronic device includes a processor having a micro-operation queue, multiple scheduler entries, and scheduler compression logic. When a pair of micro-operations in the micro-operation queue is compressible in accordance with one or more compressibility rules, the scheduler compression logic acquires the pair of micro-operations from the micro-operation queue and stores information from both micro-operations of the pair of micro-operations into different portions in a single scheduler entry. In this way, the scheduler compression logic compresses the pair of micro-operations into the single scheduler entry.

公开(公告)号：US11508124B2

公开(公告)日：2022-11-22

申请号：US17121965

申请日：2020-12-15

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Nishank Pathak

IPC: G06T17/20 ,  G06T15/00

Abstract: A processing system includes hull shader circuitry that launches thread groups including one or more primitives. The hull shader circuitry also generates tessellation factors that indicate subdivisions of the primitives. The processing system also includes throttling circuitry that estimates a primitive launch time interval for the domain shader based on the tessellation factors and selectively throttles launching of the thread groups from the hull shader circuitry based on the primitive launch time interval of the domain shader and a hull shader latency. In some cases, the throttling circuitry includes a first counter that is incremented in response to launching a thread group from the buffer and a second counter that modifies the first counter based on a measured latency of the domain shader.

公开(公告)号：US11507641B2

公开(公告)日：2022-11-22

申请号：US16428903

申请日：2019-05-31

Applicant: Advanced Micro Devices, Inc.

Inventor： Majed Valad Beigi ,  Amin Farmahini-Farahani ,  Sudhanva Gurumurthi

IPC: G06F17/16 ,  G01K3/14 ,  G01K3/10

Abstract: Techniques for performing in-memory matrix multiplication, taking into account temperature variations in the memory, are disclosed. In one example, the matrix multiplication memory uses ohmic multiplication and current summing to perform the dot products involved in matrix multiplication. One downside to this analog form of multiplication is that temperature affects the accuracy of the results. Thus techniques are provided herein to compensate for the effects of temperature increases on the accuracy of in-memory matrix multiplications. According to the techniques, portions of input matrices are classified as effective or ineffective. Effective portions are mapped to low temperature regions of the in-memory matrix multiplier and ineffective portions are mapped to high temperature regions of the in-memory matrix multiplier. The matrix multiplication is then performed.

公开(公告)号：US11507522B2

公开(公告)日：2022-11-22

申请号：US16706421

申请日：2019-12-06

Applicant: Advanced Micro Devices, Inc.

Inventor： Sooraj Puthoor ,  Kishore Punniyamurthy ,  Onur Kayiran ,  Xianwei Zhang ,  Yasuko Eckert ,  Johnathan Alsop ,  Bradford Michael Beckmann

IPC: G06F13/18 ,  G06F13/16

Abstract: Systems, apparatuses, and methods for implementing memory request priority assignment techniques for parallel processors are disclosed. A system includes at least a parallel processor coupled to a memory subsystem, where the parallel processor includes at least a plurality of compute units for executing wavefronts in lock-step. The parallel processor assigns priorities to memory requests of wavefronts on a per-work-item basis by indexing into a first priority vector, with the index generated based on lane-specific information. If a given event is detected, a second priority vector is generated by applying a given priority promotion vector to the first priority vector. Then, for subsequent wavefronts, memory requests are assigned priorities by indexing into the second priority vector with lane-specific information. The use of priority vectors to assign priorities to memory requests helps to reduce the memory divergence problem experienced by different work-items of a wavefront.

公开(公告)号：US11507517B2

公开(公告)日：2022-11-22

申请号：US17033212

申请日：2020-09-25

Applicant: Advanced Micro Devices, Inc.

Inventor： Amit Apte ,  Ganesh Balakrishnan

IPC: G06F12/0895

Abstract: Disclosed is a cache directory including one or more cache directories configurable to interchange within each cache directory entry at least one bit between a first field and a second field to change the size of the region of memory represented and the number of cache lines tracked in the cache subsystem.