公开(公告)号：US11215759B2

公开(公告)日：2022-01-04

申请号：US16889164

申请日：2020-06-01

Applicant: STMicroelectronics SA

Inventor： Frederic Gianesello ,  Ophelie Foissey ,  Cedric Durand

IPC: G02B6/27 ,  G02B6/34

Abstract: An integrated optoelectronic or optical device is formed by a polarization-splitting grating coupler including two optical waveguides, a common optical coupler and flared optical transitions between the optical coupler and the optical waveguides. The optical coupler is configured for supporting input/output of optical waves. A first region of the optical coupler lies at a distance from the flared optical transitions. The first region includes a first recessed pattern. Second regions of the optical coupler lie between the first region and the flared optical transitions, respectively, in an adjoining relationship. The second regions include a second recessed pattern different from the first recessed pattern.

公开(公告)号：US20210365059A1

公开(公告)日：2021-11-25

申请号：US17393658

申请日：2021-08-04

Applicant: STMicroelectronics SA

Inventor： Lionel VOGT ,  Eoin Padraig O HANNAIDH

IPC: G05F1/575 ,  G05F1/565

Abstract: A low-dropout regulator includes a power stage having an output terminal coupled to a load circuit operable in different operating modes in which it receives different output currents. An error amplifier has a first input coupled to a reference voltage and an output coupled to an input terminal of the power stage. A compensation circuit includes a first stage with an RC filter coupled to the input terminal of the power stage, and generating an initial compensation voltage. A second stage includes a first transistor coupled between a supply voltage and a second node, and controlled by a complementary control signal, a high-side capacitor coupled between the second node and ground, and a third transistor coupled between the initial compensation voltage and the second node, and controlled by a control signal representative of the current operating mode of the load circuit.

公开(公告)号：US11138749B2

公开(公告)日：2021-10-05

申请号：US16548138

申请日：2019-08-22

Applicant: STMicroelectronics SA

Inventor： Manu Alibay ,  Olivier Pothier ,  Victor Macela ,  Alain Bellon ,  Arnaud Bourge

IPC: G06K9/00 ,  G06T7/521 ,  G01S17/08 ,  G06T7/55 ,  G06T7/593 ,  H04N13/271 ,  H04N13/254 ,  H04N13/207 ,  H04N13/00 ,  H04N13/204

Abstract: The method of determination of a depth map of a scene comprises generation of a distance map of the scene obtained by time of flight measurements, acquisition of two images of the scene from two different viewpoints, and stereoscopic processing of the two images taking into account the distance map. The generation of the distance map includes generation of distance histograms acquisition zone by acquisition zone of the scene, and the stereoscopic processing includes, for each region of the depth map corresponding to an acquisition zone, elementary processing taking into account the corresponding histogram.

公开(公告)号：US11128057B2

公开(公告)日：2021-09-21

申请号：US16296022

申请日：2019-03-07

Applicant: STMICROELECTRONICS SA

Inventor： Frederic Gianesello

IPC: H01Q21/06 ,  H01Q21/24 ,  H01Q13/02 ,  H04B5/00 ,  H01P5/02 ,  H01Q21/08 ,  H01Q21/28 ,  H01Q1/52

Abstract: A connector includes a first antenna configured to transmit first signals in a first direction and with a first polarization, a second antenna coupled to the first antenna and configured to transmit second signals in a second direction that is parallel to the first direction and with a second polarization that is orthogonal to the first polarization, and a third antenna coupled to the first and second antennas and configured to transmit third signals in a third direction that is parallel to the first direction and with the first polarization, wherein the second antenna is positioned between the first and third antennas.

公开(公告)号：US20210278287A1

公开(公告)日：2021-09-09

申请号：US17192438

申请日：2021-03-04

Applicant: STMicroelectronics SA

Inventor： Philippe GALY ,  Renan LETHIECQ

IPC: G01K7/01 ,  H01C7/00 ,  G01K7/25 ,  G05F3/24

Abstract: An electronic device includes a module that delivers a positive temperature coefficient output voltage at an output terminal. A thermistor includes a first MOS transistor operating in weak inversion mode and having a negative temperature coefficient drain-source resistance and whose source is coupled to the output terminal. A current source coupled to the output terminal operates to impose the drain-source current of the first transistor.

公开(公告)号：US10978487B2

公开(公告)日：2021-04-13

申请号：US16288737

申请日：2019-02-28

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics SA

Inventor： Hassan El Dirani ,  Pascal Fonteneau

IPC: H01L29/76 ,  H01L27/12 ,  H02M7/5387 ,  H01L29/417 ,  H03K19/10 ,  H03K19/00 ,  H03K19/094

Abstract: An inverter includes a semiconductor substrate. A Z2-FET switch is disposed at a first surface of the semiconductor substrate and a further switch is disposed at the first surface of the semiconductor substrate. The further switch and the Z2-FET switch have current paths coupled between a first reference terminal and a second reference terminal.

公开(公告)号：US10978340B2

公开(公告)日：2021-04-13

申请号：US16384147

申请日：2019-04-15

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics SA

Inventor： Didier Dutartre ,  Jean-Pierre Carrere ,  Jean-Luc Huguenin ,  Clement Pribat ,  Sarah Kuster

IPC: H01L27/12 ,  H01L27/146 ,  H01L27/06 ,  H01L27/07 ,  H01L29/06 ,  H01L29/10 ,  H01L21/768 ,  H01L21/8234 ,  H01L21/84 ,  H01L21/762 ,  H01L21/74 ,  H01L21/02

Abstract: A silicon on insulator substrate includes a semiconductor bulk handle wafer, an insulating layer on said semiconductor bulk handle wafer and a semiconductor film on said insulating layer. An opening extends completely through the semiconductor film and insulating layer to expose a surface of the semiconductor bulk handle wafer. Epitaxial material fills the opening and extends on said semiconductor film, with the epitaxial material and semiconductor film forming a thick semiconductor film. A trench isolation surrounds a region of the thick semiconductor film to define an electrical contact made to the semiconductor bulk handle wafer through the opening.

公开(公告)号：US10976494B2

公开(公告)日：2021-04-13

申请号：US16662810

申请日：2019-10-24

Applicant: STMicroelectronics SA

Inventor： Cédric Durand ,  Frédéric Gianesello ,  Folly Eli Ayi-Yovo

IPC: B23K26/364 ,  C03C17/09 ,  G02B6/136 ,  G02B6/138 ,  G02B6/30 ,  C03C23/00 ,  B23K26/402 ,  B23K26/0622 ,  B23K103/00 ,  G02B6/12

Abstract: A method of manufacturing an optical device is disclosed. The method includes scanning along a curved path at a first surface of a glass plate with a laser beam directed orthogonally to the first surface to form a trench according to a pattern of a waveguide. The curved path is coincident with a longitudinal axis of the waveguide. The method further includes filling the trench with a material having an index different from that of glass to form the waveguide and, after filling the trench, depositing a cladding layer.

公开(公告)号：US10944257B2

公开(公告)日：2021-03-09

申请号：US15952466

申请日：2018-04-13

Applicant: STMicroelectronics International N.V. ,  STMicroelectronics SA

Inventor： Radhakrishnan Sithanandam ,  Divya Agarwal ,  Jean Jimenez ,  Malathi Kar

IPC: H02H9/02 ,  H02H9/04 ,  H01L27/02 ,  H01L27/07 ,  H01L29/06

Abstract: Electrostatic discharge (ESD) protection is provided in using a supply clamp circuit using an ESD event actuated SCR device. The SCR device may include an embedded field effect transistor (FET) having an insulated gate that receives a trigger signal from an ESD detection circuit. The SCR device may alternatively include a variable substrate resistor having an insulated gate that receives a trigger signal from an ESD detection circuit.

公开(公告)号：US20210020663A1

公开(公告)日：2021-01-21

申请号：US16926128

申请日：2020-07-10

Applicant: STMicroelectronics SA

Inventor： Philippe GALY ,  Thomas BEDECARRATS

IPC: H01L27/12

Abstract: An integrated circuit includes a MOS transistor that is located in and on a semiconductor film of a silicon-on-insulator (SOI) substrate. The SOI substrate has, below a buried insulator layer, a first back gate region and two first auxiliary regions that are located, respectively, below source and drain contact regions of the MOS transistor. The conductivity type of the two first auxiliary regions is the opposite the conductivity type of the first back gate region. The conductivity type of the two first auxiliary regions is identical to the conductivity type of the source and drain contact regions of the MOS transistor.