公开(公告)号：USRE36123E

公开(公告)日：1999-03-02

申请号：US492462

申请日：1995-06-15

Applicant: Flavio Scarra ,  Maurizio Gaibotti ,  Giampiero Trupia

Inventor： Flavio Scarra ,  Maurizio Gaibotti ,  Giampiero Trupia

IPC: G01R31/3183 ,  G01R31/317 ,  G01R31/3185 ,  H03K5/135 ,  H03K19/096

CPC classification number: G01R31/318552 ,  G01R31/31727 ,  H03K5/135

Abstract: The circuit comprises a first switching circuit which receives at an input a system clock normally provided for the operation of the integrated circuit and produces at an output a machine clock normally coincident with the system clock, circuitry for clamping the first switching circuit responsive to a firing signal of the serial operational analysis device determines which state the machine clock is clamped in and second switching circuit which receives at an input the system clock and is responsive to the firing signal to produce a scanning clock which repeats the system clock in an inverted or non-inverted manner according to the state in which the machine clock has been clamped.

Abstract translation: 电路包括第一开关电路，其在输入端接收通常为集成电路的操作提供的系统时钟，并在输出端产生通常与系统时钟一致的机器时钟，用于响应于点火而钳位第一开关电路的电路 串行操作分析装置的信号确定机器时钟被钳位的状态以及在输入端接收系统时钟并响应于点火信号产生扫描时钟的第二切换电路，该扫描时钟以反相或非反相重复系统时钟 根据机器时钟被钳位的状态反转。

公开(公告)号：US5870495A

公开(公告)日：1999-02-09

申请号：US584529

申请日：1996-01-11

Applicant: Massimo Mancuso ,  Paolo Moretti ,  Rinaldo Poluzzi ,  Gianguido Rizzotto

Inventor： Massimo Mancuso ,  Paolo Moretti ,  Rinaldo Poluzzi ,  Gianguido Rizzotto

IPC: G06T7/60 ,  G06K9/46

CPC classification number: G06K9/4633

Abstract: A method for recognizing geometric shapes in an image using fuzzy logic. The method includes determining an edge in the image and a gradient of the edge. The gradient is corrected by virtue of a first fuzzy logic process, and the number of points that belong to the curve are determined by virtue of a second fuzzy logic process. A fuzzy device for the recognition of geometric shapes in images that implementing the method includes an edge detector, a fuzzy gradient corrector to correct the gradient, and a fuzzy vote attributor to determine the number of points that belong to the curve.

Abstract translation: 一种使用模糊逻辑识别图像中几何形状的方法。 该方法包括确定图像中的边缘和边缘的梯度。 通过第一模糊逻辑过程校正梯度，并且通过第二模糊逻辑过程来确定属于该曲线的点的数量。 用于识别实现该方法的图像中的几何形状的模糊装置包括边缘检测器，用于校正梯度的模糊梯度校正器和用于确定属于该曲线的点数的模糊投票属性。

公开(公告)号：US5864513A

公开(公告)日：1999-01-26

申请号：US827409

申请日：1997-03-27

Applicant: Luigi Pascucci

Inventor： Luigi Pascucci

IPC: G11C16/28 ,  G11C13/00

CPC classification number: G11C16/28

Abstract: A system for determining the programmed/non-programmed status of a memory cell includes a first branch for connecting a first load and a memory cell matrix and a second branch for connecting a second load and at least one virgin reference memory cell. A circuit for selecting a memory cell of the memory matrix and a circuit for selecting at least one virgin reference cell are included. Each one of the first and second branches has a transistor for enabling a flow of current, respectively, between the first load and the second load and the memory cell matrix and the at least one reference memory cell. The enabling transistors are controlled, respectively, by a first biasing structure and by a second biasing structure. The system includes at least one transistor for redistributing the current of the load on the first branch, which is connected in parallel to the enabling transistor, and a first equalization transistor that is controlled by a precharge signal for the equalization of opposite nodes of the first and second branches. The at least one current redistribution transistor provides a current imbalance in the first load and in the second load in order to sense a difference in conductivity between a memory cell of the memory matrix and the at least one reference cell in order to determine the programmed or non-programmed status of the memory cell of the memory matrix.

Abstract translation: 用于确定存储器单元的编程/非编程状态的系统包括用于连接第一负载和存储单元矩阵的第一分支和用于连接第二负载和至少一个处女参考存储单元的第二分支。 包括用于选择存储器矩阵的存储单元的电路和用于选择至少一个处女参考单元的电路。 第一和第二分支中的每一个分支具有晶体管，用于分别在第一负载和第二负载与存储单元矩阵和至少一个参考存储单元之间流动电流。 分别通过第一偏压结构和第二偏压结构来控制使能晶体管。 该系统包括至少一个晶体管，用于重新分配与启用晶体管并联连接的第一分支上的负载电流，以及由预充电信号控制的第一均衡晶体管，用于均衡第一 和第二分支。 所述至少一个电流再分配晶体管在第一负载和第二负载中提供电流不平衡，以便感测存储器矩阵的存储单元与至少一个参考单元之间的导电差异，以便确定编程或 存储器矩阵的存储单元的非编程状态。

公开(公告)号：US5864500A

公开(公告)日：1999-01-26

申请号：US835296

申请日：1997-04-07

Applicant: Luigi Pascucci

Inventor： Luigi Pascucci

IPC: G11C14/00 ,  G11C11/34

CPC classification number: G11C14/00

Abstract: The present invention concerns an auto-saving circuit for programming configuration elements of non-volatile memory cells organized in a cells matrix in a memory device integrated on a semiconductor. The auto-saving circuit is inserted between a first and a second power supply reference voltage and is powered also by programming voltages generated inside the memory device to produce at an output programming signals of the configuration elements. The auto-saving circuit includes a first and a second circuit portion, one for each signal output and each powered by a respective programming voltage and each including a switching network with at least one high threshold transistor and decoupling elements to give inertia to the circuit against electrostatic discharges or accidental power supply variations.

Abstract translation: 本发明涉及用于编程组合在集成在半导体上的存储器件中的单元矩阵中的非易失性存储单元的配置元件的自动保存电路。 自动保存电路插入在第一和第二电源参考电压之间，并且还通过在存储器件内部产生的编程电压来供电，以在配置元件的输出编程信号产生。 自动保存电路包括第一和第二电路部分，每个信号输出一个，每个由相应的编程电压供电，每个包括具有至少一个高阈值晶体管和去耦元件的开关网络，以使电路的惯性反对 静电放电或意外电源变化。

公开(公告)号：US5859795A

公开(公告)日：1999-01-12

申请号：US791348

申请日：1997-01-30

Applicant: Paolo Rolandi

Inventor： Paolo Rolandi

IPC: G11C11/41 ,  G06F12/16 ,  G11C11/56 ,  G11C7/00

CPC classification number: G11C11/5642 ,  G11C11/5621 ,  G11C11/5628 ,  G11C2211/5641 ,  G11C29/00

Abstract: The present invention relates to a memory circuit of the multi-level type, i.e. a memory circuit having a plurality of memory elements, each adapted to store more than one binary information unit, wherein the memory elements are utilized for storing a number of binary information units tied to an acceptable error rate for a particular application: typically, one bit where a low error rate is sought, and two bits where a higher error rate can be accepted.

Abstract translation: 本发明涉及多电平型存储器电路，即具有多个存储器元件的存储器电路，每个存储器电路适于存储多于一个二进制信息单元，其中存储元件用于存储多个二进制信息 绑定到特定应用的可接受错误率的单元：通常，寻求低错误率的一个位和可以接受更高错误率的两个位。

公开(公告)号：US5859608A

公开(公告)日：1999-01-12

申请号：US722377

申请日：1996-09-30

Applicant: Giona Fucili ,  Lorenzo Papillo ,  Andrea Pasquino ,  Annamaria Rossi ,  Alberto Gola

Inventor： Giona Fucili ,  Lorenzo Papillo ,  Andrea Pasquino ,  Annamaria Rossi ,  Alberto Gola

IPC: H03M1/46 ,  H03M1/34

CPC classification number: H03M1/462

Abstract: A successive approximation shift register without redundancy for a finite-state machine of the sequential type, is also effective to store the machine states. The shift register comprises a chain of logic circuits of the bistable type (FF0,FF1, . . . ) having an input stage with selectable signal inputs which are feedback connected through logic OR gate circuits (OR0,OR1, . . . ,OR6).

Abstract translation: 对于顺序类型的有限状态机，没有冗余的逐次逼近移位寄存器对于存储机器状态也是有效的。 移位寄存器包括具有输入级的双稳态型（FF0，FF1 ...）的逻辑电路链，其具有通过逻辑或门电路（OR0，OR1，...，OR6）反馈连接的可选信号输入， 。

公开(公告)号：US5852314A

公开(公告)日：1998-12-22

申请号：US643152

申请日：1996-04-30

Applicant: Riccardo Depetro ,  Claudio Contiero ,  Antonio Andreini

Inventor： Riccardo Depetro ,  Claudio Contiero ,  Antonio Andreini

IPC: H01L21/8238 ,  H01L27/06 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/423 ,  H01L29/78 ,  H01L29/76 ,  H01L23/58 ,  H01L29/94

CPC classification number: H01L29/0878 ,  H01L27/0623 ,  H01L27/0922 ,  H01L29/1083 ,  H01L29/7816 ,  H01L29/7835 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/42368

Abstract: N-channel LDMOS and p-channel MOS devices for high voltage integrated in a BiCMOS integrated circuit and exploiting a RESURF condition are provided with a buried region of the same type of conductivity of the epitaxial layer and a doping level intermediate between the doping level of the epitaxial layer and the doping level of a well region. The devices may be configured as source or drain followers without problems.

Abstract translation: 集成在BiCMOS集成电路中并利用RESURF条件的用于高电压的N沟道LDMOS和p沟道MOS器件具有与外延层相同类型的导电性的掩埋区域和掺杂水平之间的掺杂水平 外延层和阱区的掺杂水平。 这些器件可能被配置为源或漏源从器件而没有问题。

公开(公告)号：US5851871A

公开(公告)日：1998-12-22

申请号：US675520

申请日：1996-07-03

Applicant: Danilo Re

Inventor： Danilo Re

IPC: H01L21/02 ,  H01L21/8238 ,  H01L27/06 ,  H01L21/8242

CPC classification number: H01L28/40 ,  H01L21/8238 ,  H01L27/0688

Abstract: A process for manufacturing integrated capacitors in CMOS technology, comprising the steps of: producing, in a substrate of semiconductor material having a first type of conductivity, at least one well with the opposite type of conductivity, defining the active areas, producing insulation regions, depositing a first conducting layer of polycrystalline silicon adapted to form the gate regions and the lower plates of the capacitors, depositing a layer of silicon oxide at low temperature, to form the dielectric of the capacitors, depositing a second layer of polycrystalline silicon to form the second plate of the capacitors, shaping the polycrystalline silicon and silicon oxide layers, implanting and diffusing the source and drain regions of the CMOS transistors, providing the insulation layer, the metallic connecting layer, and final covering with a layer of protective insulation.

Abstract translation: 一种用于制造CMOS技术的集成电容器的方法，包括以下步骤：在具有第一类型导电性的半导体材料的衬底中制造具有相反导电性的至少一个阱，限定有源区，产生绝缘区， 沉积适于形成电容器的栅极区域和下部板的多晶硅的第一导电层，在低温下沉积氧化硅层，以形成电容器的电介质，沉积第二层多晶硅以形成 电容器的第二板，对多晶硅和氧化硅层进行成形，注入并扩散CMOS晶体管的源极和漏极区域，提供绝缘层，金属连接层以及具有保护绝缘层的最终覆盖层。

公开(公告)号：US5850361A

公开(公告)日：1998-12-15

申请号：US628587

申请日：1996-04-04

Applicant: Luigi Pascucci

Inventor： Luigi Pascucci

IPC: G11C16/04 ,  G11C29/00

CPC classification number: G11C29/802 ,  G11C16/0433

Abstract: A coding device including an array of multibit registers, each being composed of a plurality of programmable nonvolatile memory cells connected to an OR configuration to a common sensing line of the register to which a single reading circuit is associated. A first, select/enable bus (SELbus) controls the connection of only one at a time of said programmable memory cells to said common sensing line of each multibit register. To each wire of a second, configuring bus (CODE bus) are connected in common the current terminals of as many programming transistors as the memory cells that compose each register, and to each wire of a third, contingently programming bus (PG bus) are connected the gates of the programming transistors of memory cells of the same order of said registers.

Abstract translation: 一种包括多位寄存器阵列的编码装置，每一个由多个可编程非易失性存储单元构成，所述多个可编程非易失存储单元连接到与配置相关联的寄存器的公共感测线的OR配置。 第一个选择/使能总线（SELbus）控制所述可编程存储器单元每次只有一个与每个多位寄存器的所述公共感测线的连接。 对于一秒钟的每根线，配置总线（CODE总线）与构成每个寄存器的存储器单元的编程晶体管的当前端子共同连接，并且第三个偶然编程总线（PG总线）的每个线都是 连接所述寄存器相同顺序的存储器单元的编程晶体管的栅极。

公开(公告)号：US5850092A

公开(公告)日：1998-12-15

申请号：US833925

申请日：1997-04-10

Applicant: Paolo Cappelletti

Inventor： Paolo Cappelletti

IPC: G11C17/00 ,  G11C11/00 ,  G11C16/04 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC classification number: H01L27/11517 ,  G11C11/005 ,  G11C16/0408 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524

Abstract: Cost-efficient integration of a fully-featured EEPROM memory block in a FLASH-EPROM memory device, fabricated according to a low supply voltage and low power consumption FLASH-EPROM process, is made possible by a special structure of the EEPROM cells whereby the capacitive coupling between the floating gate and the control gate of the cell is realized over the field oxide adjacent to the active area of the cell. The process of the invention permits an optimized modulation of the thicknesses of the different tunnel and gate oxides of the FLASH-EPROM and EEPROM cells, as well as of the transistors of the peripheral circuitry of the two memory blocks destined to work with a relatively low supply voltage or with a boosted voltage.