公开(公告)号：US20220391171A1

公开(公告)日：2022-12-08

申请号：US17744337

申请日：2022-05-13

Applicant: STMicroelectronics (Rousset) SAS ,  STMicroelectronics (Alps) SAS

Inventor： Fabrice Romain ,  Fabien Journet

IPC: G06F7/523

Abstract: In an embodiment, after a first phase of multiplication, in an electronic multiplication circuit, of a first operand by a second operand leading to a successive delivery of least significant words of the result of the first multiplication, a second multiplication, of the first operand by a supplementary operand is implemented in the electronic multiplication circuit, during a second phase of multiplication. The supplementary operands are not all identical.

公开(公告)号：US11522057B2

公开(公告)日：2022-12-06

申请号：US17100559

申请日：2020-11-20

Applicant: STMicroelectronics (Rousset) SAS ,  STMicroelectronics (Crolles 2) SAS

Inventor： Franck Julien ,  Stephan Niel ,  Leo Gave

IPC: H01L29/40 ,  H01L29/51 ,  H01L29/66

Abstract: A method for manufacturing an electronic device includes locally implanting ionic species into a first region of a silicon nitride layer and into a first region of an electrically insulating layer located under the first region of the silicon nitride layer. A second region of the silicon nitride layer and a region of the electrically insulating layer located under the second region of the silicon nitride layer are protected from the implantation. The electrically insulating layer is disposed between a semi-conducting substrate and the silicon nitride layer. At least one trench is formed extending into the semi-conducting substrate through the silicon nitride layer and the electrically insulating layer. The trench separates the first region from the second region of the electrically insulating layer. The electrically insulating layer is selectively etched, and the etch rate of the electrically insulating layer in the first region is greater than the etch rate in the second region.

公开(公告)号：US20220369006A1

公开(公告)日：2022-11-17

申请号：US17735968

申请日：2022-05-03

Applicant: STMICROELECTRONICS LTD ,  STMICROELECTRONICS (ROUSSET) SAS ,  STMicroelectronics Razvoj Polprevodnikov D.O.O.

Inventor： Nicolas CORDIER ,  Chia Hao CHEN ,  Karel BLAHA

IPC: H04Q9/06

Abstract: Provided is a device comprising a frequency demodulator and an amplitude demodulator. The device is configured to use, in a first mode, both the frequency demodulator and the amplitude demodulator in parallel and to activate a radio frequency identification (RFID) card mode or a Qi charger mode based on results provided by said demodulators.

公开(公告)号：US20220367497A1

公开(公告)日：2022-11-17

申请号：US17734963

申请日：2022-05-02

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Francois TAILLIET ,  Roberto SIMOLA ,  Philippe BOIVIN

IPC: H01L27/11529 ,  H01L27/11524

Abstract: The integrated circuit of a non-volatile memory of the electrically erasable and programmable type includes memory cells, each memory cell having a state transistor including a gate structure comprising a control gate and a floating gate disposed on a face of a semiconductor well, as well as a source region and a drain region in the semiconductor well. The drain region includes a first capacitive implant region positioned predominantly under the gate structure and a lightly doped region positioned predominantly outside the gate structure. The source region includes a second capacitive implant region positioned predominantly outside the gate structure, the source region not including a lightly doped region.

公开(公告)号：US20220321124A1

公开(公告)日：2022-10-06

申请号：US17846362

申请日：2022-06-22

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Nicolas Borrel ,  Jimmy Fort ,  Mathieu Lisart

IPC: H03K19/003 ,  H03F3/45 ,  H03K19/00 ,  H03K19/17736 ,  H03L7/097

Abstract: A physically unclonable function device includes a set of diode-connected MOS transistors having a random distribution of respective threshold voltages. A first circuit is configured to impose, on each first transistor, a fixed respective gate voltage regardless of the value of a current flowing in this first transistor. A second circuit is configured to impose, on each second transistor, a fixed respective gate voltage regardless of the value of a current flowing in this second transistor. A current mirror stage is coupled between the first circuit and the second circuit and is configured to deliver the reference current from a sum of the currents flowing in the first transistors. A comparator is configured to deliver a signal whose level depends on a comparison between a first current obtained from a reference current based on the first transistors and a second current of the second transistors.

公开(公告)号：US11456853B2

公开(公告)日：2022-09-27

申请号：US16810434

申请日：2020-03-05

Applicant: STMICROELECTRONICS (ROUSSET) SAS

Inventor： Ibrahima Diop ,  Yanis Linge

IPC: H04L9/00 ,  G06F7/72 ,  G06F7/504 ,  G06F7/525

Abstract: Cryptographic circuitry, in operation, performs a calculation on a first number and a second number. The performing of the calculation is protected by breaking the second number into a plurality of third numbers, a sum of values of the third numbers being equal to a value of the second number. The calculation is performed bit by bit for each rank of the third numbers. Functional circuitry, coupled to the cryptographic circuitry, uses a result of the calculation.

公开(公告)号：US20220239335A1

公开(公告)日：2022-07-28

申请号：US17575523

申请日：2022-01-13

Applicant: STMicroelectronics Ltd ,  STMicroelectronics (Rousset) SAS

Inventor： Nicolas CORDIER ,  Chia-Hao CHEN

IPC: H04B5/00 ,  H04W24/08

Abstract: A method is provided that is implemented by a first NFC device configured in reader mode. The method includes evaluating an information about the coupling between the first NFC device and a second NFC device configured in card mode, as a function of the position of an antenna of the first NFC device with respect to an antenna of the second NFC device. The method further includes indicating the information by a user interface of the first device.

公开(公告)号：US11386963B2

公开(公告)日：2022-07-12

申请号：US17166107

申请日：2021-02-03

Applicant: STMicroelectronics (Rousset) SAS

Inventor： François Tailliet ,  Marc Battista

IPC: G11C16/04 ,  G11C16/14 ,  G11C16/26 ,  G11C16/30

Abstract: The memory device of the electrically-erasable programmable read-only memory type comprises write circuitry designed to carry out a write operation in response to receiving a command for writing at least one selected byte in at least one selected memory word of the memory plane, the write operation comprising an erase cycle followed by a programming cycle, and configured for generating, during the erase cycle, an erase voltage in the memory cells of all the bytes of the at least one selected memory word, and an erase inhibit potential configured, with respect to the erase voltage, for preventing the erasing of the memory cells of the non-selected bytes of the at least one selected memory word, which are not the at least one selected byte.

公开(公告)号：US11354238B2

公开(公告)日：2022-06-07

申请号：US16691957

申请日：2019-11-22

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Laurent Folliot ,  Pierre Demaj

IPC: G06N3/04 ,  G06F12/02 ,  G06F12/06

Abstract: A method can be used to determine an overall memory size of a global memory area to be allocated in a memory intended to store input data and output data from each layer of a neural network. An elementary memory size of an elementary memory area intended to store the input data and the output data from the layer is determined for each layer. The elementary memory size is in the range between a memory size for the input data or output data from the layer and a size equal to the sum of the memory size for the input data and the memory size for the output data from the layer. The overall memory size is determined based on the elementary memory sizes associated with the layers. The global memory area contains all the elementary memory areas.

公开(公告)号：US20220166415A1

公开(公告)日：2022-05-26

申请号：US17524306

申请日：2021-11-11

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Vincent Binet ,  Michel Cuenca ,  Ludovic Girardeau

IPC: H03K4/50 ,  H03K3/037 ,  H03K5/24

Abstract: Series of first ramps and second ramps are generated. A circuit delivers a first signal representative of the comparison of each first ramp with a set point and delivers a second signal representative of the comparison of each second ramp with the set point. Based on the first and second signals: a first ramp is stopped and a second ramp is started when the first ramp reaches the set point, and a second ramp is stopped and a first ramp is started when the second ramp reaches the set point. The value of the set point is modulated in response a maximum value of the first/second last ramp compared with the set point.