公开(公告)号：US20240405019A1

公开(公告)日：2024-12-05

申请号：US18327107

申请日：2023-06-01

Applicant: GlobalFoundries U.S. Inc.

Inventor： Marvin G.L. Montaque ,  Cathryn J. Christiansen ,  Craig B. Beucler ,  Timothy W. Kemerer

IPC: H01L27/06 ,  H01L21/8249

Abstract: A structure includes a first gate structure spaced from a second gate structure in a field effect transistor (FET) area of a substrate. A polysilicon resistor is in a space between the first gate structure and the second gate structure. The polysilicon resistor has a lower surface that is farther from the substrate than lower surfaces of the polysilicon bodies of the first and second gate structures. The polysilicon resistor may have a different polarity dopant compared to at least one of the polysilicon bodies of the first and second gate structures.

公开(公告)号：US20240402426A1

公开(公告)日：2024-12-05

申请号：US18203321

申请日：2023-05-30

Applicant: GlobalFoundries U.S. Inc.

Inventor： Yusheng Bian ,  Ryan Sporer ,  Karen Nummy

IPC: G02B6/124 ,  G02B6/13

Abstract: Structures for a photonics chip that include a reflector and methods of forming such structures. The structure comprises a reflector including a dielectric layer on a semiconductor substrate, a plurality of trenches in the dielectric layer, and a reflector layer. Each trench includes a plurality of sidewalls, and the reflector layer includes a portion on the sidewalls of each trench. The structure further comprises a photonic component over the reflector.

公开(公告)号：US12159926B2

公开(公告)日：2024-12-03

申请号：US18373598

申请日：2023-09-27

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Haiting Wang ,  Alexander Derrickson ,  Jagar Singh ,  Vibhor Jain ,  Andreas Knorr ,  Alexander Martin ,  Judson R. Holt ,  Zhenyu Hu

IPC: H01L29/735 ,  H01L29/08 ,  H01L29/417 ,  H01L29/66 ,  H01L29/737

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a lateral bipolar transistor and methods of manufacture. A structure includes: an intrinsic base comprising semiconductor material in a channel region of a semiconductor substrate; an extrinsic base vertically above the intrinsic base; a raised collector region on the semiconductor substrate and laterally connected to the intrinsic base; and a raised emitter region on the semiconductor substate and laterally connected to the intrinsic base.

公开(公告)号：US20240363741A1

公开(公告)日：2024-10-31

申请号：US18767418

申请日：2024-07-09

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Jagar SINGH

IPC: H01L29/735 ,  H01L29/08 ,  H01L29/10

CPC classification number: H01L29/735 ,  H01L29/0808 ,  H01L29/0821 ,  H01L29/1008

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to bipolar transistors and methods of manufacture. The structure includes: an emitter in a semiconductor substrate; a collector in the semiconductor substrate; a base contact region in the semiconductor substrate and adjacent to the collector and the emitter; and a shallow trench isolation structure overlapping the base contact region and separating the base contact region from the emitter and the collector.

公开(公告)号：US20240361529A1

公开(公告)日：2024-10-31

申请号：US18139128

申请日：2023-04-25

Applicant: GlobalFoundries U.S. Inc.

Inventor： Keith Donegan ,  Thomas Houghton ,  Yusheng Bian ,  Karen Nummy ,  Kevin Dezfulian ,  Takako Hirokawa

IPC: G02B6/30 ,  G02B6/42

CPC classification number: G02B6/305 ,  G02B6/42 ,  G02B6/4206

Abstract: Structures including a cavity adjacent to an edge coupler and methods of forming such structures. The structure comprises a semiconductor substrate including a cavity with a sidewall, a dielectric layer on the semiconductor substrate, and an edge coupler on the dielectric layer. The structure further comprises a fill region including a plurality of fill features adjacent to the edge coupler. The fill region includes a reference marker at least partially surrounded by the plurality of fill features, and the reference marker has a perimeter that surrounds a surface area of the dielectric layer, and the surface area overlaps with a portion of the sidewall of the cavity.

公开(公告)号：US12131904B2

公开(公告)日：2024-10-29

申请号：US17934220

申请日：2022-09-22

Applicant: GlobalFoundries U.S. Inc.

Inventor： Ramsey Hazbun ,  Alvin J. Joseph ,  Siva P. Adusumilli ,  Cameron Luce

IPC: H01L21/02

CPC classification number: H01L21/02433 ,  H01L21/02381 ,  H01L21/02639 ,  H01L21/02647

Abstract: Disclosed are semiconductor structure embodiments of a semiconductor-on-insulator region on a bulk substrate. The semiconductor-on-insulator region includes an upper semiconductor layer above and physically separated from the substrate by insulator-containing cavities (e.g., by dielectric layer and/or a pocket of trapped air, of trapped gas, or under vacuum) and, optionally, by a lower semiconductor layer. Disclosed method embodiments include forming openings that extend vertically through the upper semiconductor layer, through a sacrificial semiconductor layer and, optionally, through a lower semiconductor layer to the substrate. Then, a selective isotropic etch process is performed to form cavities, which extend laterally off the sides of the openings into the sacrificial semiconductor layer. Depending upon the embodiments, different process steps are further performed to form plugs in at least the upper portions of the openings and insulators (including dielectric layers and/or a pocket of trapped air, of trapped gas or under vacuum) in the cavities.

公开(公告)号：US12125842B2

公开(公告)日：2024-10-22

申请号：US17831545

申请日：2022-06-03

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Anindya Nath ,  Souvick Mitra

IPC: H01L27/02 ,  H01L29/66 ,  H01L29/74

CPC classification number: H01L27/0262 ,  H01L29/66371 ,  H01L29/7412

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to vertically stacked diode-trigger silicon controlled rectifiers and methods of manufacture. The structure includes: a silicon controlled rectifier in a trap rich region of a semiconductor substrate; and at least one diode built in polysilicon (gate material) and isolated by a gate-dielectric.

公开(公告)号：US20240347652A1

公开(公告)日：2024-10-17

申请号：US18134100

申请日：2023-04-13

Applicant: GlobalFoundries U.S. Inc.

Inventor： Zhuojie Wu ,  Yusheng Bian ,  Judson R. Holt

IPC: H01L31/0232 ,  H01L31/0224 ,  H01L31/18

CPC classification number: H01L31/02327 ,  H01L31/022408 ,  H01L31/1808

Abstract: Structures including a photodetector and methods of forming a structure including a photodetector. The structure comprises a semiconductor layer comprising a crystalline semiconductor material, a waveguide core including a first sidewall and a second sidewall, and a photodetector including a light-absorbing layer, an anode, and a cathode. The light-absorbing layer includes a first portion and a second portion that are disposed on the semiconductor layer. The first portion of the light-absorbing layer is adjacent to the first sidewall of the waveguide core, and the second portion of the light-absorbing layer is adjacent to the second sidewall of the waveguide core.

公开(公告)号：US12111495B2

公开(公告)日：2024-10-08

申请号：US17828139

申请日：2022-05-31

Applicant: GlobalFoundries U.S. Inc.

Inventor： Yusheng Bian

IPC: G02B6/12 ,  G02B6/122 ,  G02B6/30

CPC classification number: G02B6/1228 ,  G02B6/12004 ,  G02B6/305 ,  G02B2006/12097 ,  G02B2006/12111 ,  G02B2006/12121 ,  G02B2006/12147

Abstract: Structures for an edge coupler and methods of fabricating a structure for an edge coupler. The structure comprises an edge coupler including a first waveguide core and a second waveguide core adjacent to the first waveguide core in a lateral direction. The first waveguide core includes a first section with a first thickness and a first plurality of segments projecting in a vertical direction from the first section. The second waveguide core includes a second section with a second thickness and a second plurality of segments projecting in the vertical direction from the second section.

公开(公告)号：US20240329299A1

公开(公告)日：2024-10-03

申请号：US18126745

申请日：2023-03-27

Applicant: GlobalFoundries U.S. Inc.

Inventor： Yusheng Bian

IPC: G02B6/12 ,  G02B6/122 ,  G02B6/125

CPC classification number: G02B6/12004 ,  G02B6/1228 ,  G02B6/125 ,  G02B2006/12104 ,  G02B2006/12121

Abstract: Structures for an edge coupler and methods of forming such structures. The structure comprises a semiconductor substrate, a first waveguide core including a curved section and an end that terminates the curved section, and a second waveguide core including a section disposed adjacent to the curved section of the first waveguide core. The first waveguide core is positioned between the second waveguide core and the semiconductor substrate.