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公开(公告)号：US11411574B2
公开(公告)日：2022-08-09
申请号：US17215428
申请日：2021-03-29
摘要： A clock and data recovery circuit includes a phase detector (PD), a phase frequency detector (PFD), a multiplexer circuit, a conversion stage and an oscillator. The PD detects a difference in phase between a data signal and an oscillating signal to generate a first set of error signals. The PFD detects a difference in phase and frequency between a reference clock signal and the oscillating signal to generate a second set of error signals. The multiplexer circuit selectively outputs the first set of error signals or the second set of error signals as a third set of error signals according to a selection signal. The conversion stage determines a set of gains according to the selection signal, and converts the third set of error signals with the set of gains to generate a set of input signals. The oscillator generates the oscillating signal according to the set of input signals.
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32.发明申请公开(公告)号：US20210399733A1
公开(公告)日：2021-12-23
申请号：US17355180
申请日：2021-06-23
发明人： CHING-HSIANG CHANG , YU-HSUN CHIEN
摘要： A phase-locked loop circuit includes a phase frequency detector (PHD) circuit, a digital code generator circuit, a frequency divider and an oscillator circuit. The PFD circuit is configured to detect a difference in phase and frequency between a reference clock and a feedback clock to generate a first control signal and a second control signal. The digital code generator circuit is configured to process the second control signal to generate a digital code. The frequency divider is configured to receive an output clock to generate the feedback clock. The oscillator circuit is configured to generate the output clock according to the first control signal and the digital code. A frequency of the output clock is determined according to a first control parameter and a second control parameter of different types. The first and second control parameters are adjusted in response to the first control signal and the digital code respectively.
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33.发明申请公开(公告)号：US20210399732A1
公开(公告)日：2021-12-23
申请号：US17355178
申请日：2021-06-23
发明人： GUO-HAU LEE , HUAI-TE WANG , CHENG-LIANG HUNG
摘要： A clock and data recovery circuit includes a sampling circuit, a phase detector, a first processing circuit, a second processing circuit and an oscillator circuit. The sampling circuit is configured to sample input data according to an output clock, and generate a sampling result. The phase detector is configured to generate a detection result according to the sampling result. The first processing circuit is configured to process the sampling result to generate a first digital code. The second processing circuit is configured to accumulate a portion of the first digital code to generate a second digital code. A rate of change of a code value of the second digital code is slower than a rate of change of a code value of the first digital code. The oscillator circuit is configured to generate the output clock according to the detection result, the first digital code and the second digital code.
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公开(公告)号：US11012087B2
公开(公告)日：2021-05-18
申请号：US16701088
申请日：2019-12-02
发明人： Ching-Hsiang Chang , Yueh-Chuan Lu
摘要： A physical layer circuit at a transmitter includes an encoding chain and a plurality of flip-flops. The encoding chain, including encoding units coupled in series, is configured to encode a plurality of symbols to generate a plurality of first wire states. The encoding units are arranged to receive the symbols respectively, and convert respective symbol values of the symbols to the first wire states respectively. A first encoding unit is configured to convert a symbol value of a corresponding symbol according to a second wire state provided by a second encoding unit. The flip-flops are arranged to receive and output the first wire states according to a clock signal, respectively. One of the flip-flops is coupled between the first encoding unit and the second encoding unit. The second wire state provided by the second encoding unit is sent to the first encoding unit through the one of the flip-flops.
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公开(公告)号：US10804884B1
公开(公告)日：2020-10-13
申请号：US16749366
申请日：2020-01-22
发明人： Ming-Yen Tsai , Chun-Hsiang Lai
IPC分类号： H03L5/00 , H03K3/037 , H03K19/003 , H03K19/0185
摘要： A level shifter includes a latch circuit, an input stage, a driver stage and a control circuit. The latch circuit is configured to generate an output signal according to a signal level at a first drive node and a signal level at a second drive node. The input stage is configured to receive an input signal to adjust a signal level at a connection node. The driver stage is configured to drive the first drive node by coupling the connection node to the first drive node according to a set of control signals. The control circuit is coupled to the input stage and the driver stage. The control circuit is configured to control the driver stage to couple the connection node to the first drive node by adjusting a signal level of each control signal in the set of control signals during a level transition of the input signal.
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公开(公告)号：US09870817B2
公开(公告)日：2018-01-16
申请号：US14729853
申请日：2015-06-03
发明人： Nan-Chun Lien , David C. Yu
IPC分类号： G11C11/00 , G11C11/419
CPC分类号： G11C11/419
摘要： A SRAM module and a writing control method of the SRAM module are disclosed. The writing control method of the SRAM module is applied to a SRAM module that includes a plurality of memory cells and a bit line. The method includes: providing a first voltage as a supply voltage of the plurality of memory cells during a data retention time; decreasing a first voltage level corresponding to the data retention time of the memory cells to a second voltage level by discharging the memory cells; and performing a write process to the memory cells through the bit line. The discharge time from the first voltage level to the second voltage level is related to the number of the memory cells.
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公开(公告)号：US09496014B2
公开(公告)日：2016-11-15
申请号：US14721884
申请日：2015-05-26
发明人： David C. Yu , Nan-Chun Lien
IPC分类号： G11C11/34 , G11C8/08 , G11C7/22 , G11C11/418
CPC分类号： G11C8/08 , G11C7/22 , G11C11/418
摘要： The present invention discloses a random access memory and the memory access method thereof capable of avoiding read disturbance and increasing reading speed. An embodiment of the said random access memory comprises: a word line; a word line driving unit, coupled to the word line, operable to receive an access control signal to generate a word line enablement voltage; a voltage adjusting unit including a switch and a capacitor in which the switch is coupled to the word line and operable to receive a control signal to determine a conduction state of the switch itself and the capacitor is coupled to the switch and operable to adjust a voltage level of the word line enablement voltage according to the conduction state; and a memory unit, coupled to the word line, operable to be enabled according to the word line enablement voltage.
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公开(公告)号：US09465395B2
公开(公告)日：2016-10-11
申请号：US14662255
申请日：2015-03-19
发明人： Hung-Cheng Fan
CPC分类号： G05F1/56
摘要： A voltage generating circuit includes: (1) a driving unit having an input terminal and an output terminal, wherein the input terminal is configured to receive an input signal, wherein when the input signal is at a first logic level, power is configured to be charged from a first voltage terminal to the output terminal, and when the input signal is at a second logic level, power is configured to be discharged from the output terminal to a second voltage terminal; (2) a first switch configured to couple the second voltage terminal to a capacitance-compensating terminal based on the input signal; (3) a compensating capacitor configured to be coupled between the capacitance-compensating terminal and a third voltage terminal; and (4) a second switch configured to couple the capacitance-compensating terminal to a fourth voltage terminal based on the input signal.
摘要翻译： 电压产生电路包括：（1）具有输入端和输出端的驱动单元，其中所述输入端被配置为接收输入信号，其中当所述输入信号处于第一逻辑电平时，功率被配置为 从第一电压端子充电到输出端子，并且当输入信号处于第二逻辑电平时，功率被配置为从输出端子放电到第二电压端子; （2）第一开关，其被配置为基于所述输入信号将所述第二电压端子耦合到电容补偿端子; （3）补偿电容器，被配置为耦合在电容补偿端子和第三电压端子之间; 以及（4）第二开关，其被配置为基于所述输入信号将所述电容补偿端子耦合到第四电压端子。
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公开(公告)号：US09336865B1
公开(公告)日：2016-05-10
申请号：US14827719
申请日：2015-08-17
发明人： Li-Wei Chu , Nan-Chun Lien
IPC分类号： G11C8/00 , G11C7/00 , G11C11/419
CPC分类号： G11C11/419 , G11C8/16 , G11C11/413 , G11C11/417 , G11C11/418
摘要： A multi-port SRAM module includes a cell array comprising a plurality of cells, each having a first port and a second port; a first word line which is coupled to a plurality of cells of a target row to open and close the first port; a second word line which is coupled to the cells of the target row to open and close the second port; and a switch, which is coupled to the first word line and the second word line and couples the second word line to a reference voltage level according to a voltage level of the first word line.
摘要翻译： 多端口SRAM模块包括具有多个单元的单元阵列，每个单元具有第一端口和第二端口; 第一字线，其耦合到目标行的多个单元，以打开和关闭第一端口; 第二字线，其耦合到所述目标行的单元以打开和关闭所述第二端口; 以及开关，其耦合到所述第一字线和所述第二字线，并且根据所述第一字线的电压电平将所述第二字线耦合到参考电压电平。
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40.发明申请METHOD FOR PORTABLE DEVICE PROCESSING DATA BASED ON CLOCK EXTRACTED FROM DATA FROM HOST 有权基于从主机数据提取的时钟的便携式设备处理数据的方法公开(公告)号：US20150098542A1
公开(公告)日：2015-04-09
申请号：US14045819
申请日：2013-10-04
发明人： Yu-Sheng Yi , Ting-Chun Huang , Yuan-Hsun Chang
CPC分类号： H04L7/0331 , H03L7/087 , H04L7/0083 , H04L7/0091 , H04L7/033 , H04L7/10
摘要： A method for a first electronic device processing data based on information from a second electronic device may comprise: receiving a first signal from the second electronic device; extracting a first clock based on the first signal; adjusting an oscillator based on the first clock so as to generate a second clock; and selecting one from the first and second clocks. In an embodiment of the present invention, the first electronic device may be configured to be hot plugged into the second electronic device. The method may further comprise processing a data stream from the second electronic device based on said selecting said one from the first and second clocks. The method may further comprise transmitting a data stream to the second electronic device based on said selecting said one from the first and second clocks.
摘要翻译： 用于基于来自第二电子设备的信息处理数据的第一电子设备的方法可以包括：从第二电子设备接收第一信号; 基于第一信号提取第一时钟; 基于所述第一时钟调整振荡器以产生第二时钟; 并从第一和第二时钟中选择一个。 在本发明的实施例中，第一电子设备可被配置为热插入第二电子设备。 该方法还可以包括基于从第一和第二时钟选择所述第二电子设备的数据流来处理数据流。 该方法还可以包括基于从第一和第二时钟中选择所述第二电子设备向第二电子设备发送数据流。
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