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10 条记录 (耗时 0.017 秒)

    Integrated circuits adaptable to interchange between clock and data lanes for use in clock forward interface receiver
    1.
    发明授权
    Integrated circuits adaptable to interchange between clock and data lanes for use in clock forward interface receiver 有权

    公开(公告)号：US10387360B2

    公开(公告)日：2019-08-20

    申请号：US15805098

    申请日：2017-11-06

    申请人： M31 Technology Corporation

    发明人： Pin-Hao Feng ,  Yueh-Chuan Lu ,  Ching-Hsiang Chang

    IPC分类号： G06F13/42 ,  G06F1/10

    摘要： An integrated circuit includes a first multi-lane interface having a plurality of first lanes, a second multi-lane interface having a plurality of second lanes; a first layer of clock lane selection units arranged to select one or two of the first and second lanes and output signals on the one or two selected lanes; a second layer of clock lane selection units arranged to select the one or two selected lanes as one or two clock lane and output signals on the one or two selected clock lane; and a plurality of sampling units, each coupled to second layer of clock lane selection units, each arranged to sample one of the first and second lanes according to the signal on the selected clock lane.

    Encoding and decoding architecture for high speed data communication system and related physical layer circuit, transmitter and receiver and communication system thereof
    5.
    发明授权
    Encoding and decoding architecture for high speed data communication system and related physical layer circuit, transmitter and receiver and communication system thereof 有权

    公开(公告)号：US11012087B2

    公开(公告)日：2021-05-18

    申请号：US16701088

    申请日：2019-12-02

    申请人： M31 TECHNOLOGY CORPORATION

    发明人： Ching-Hsiang Chang ,  Yueh-Chuan Lu

    IPC分类号： H03M9/00 ,  H03M7/00

    摘要： A physical layer circuit at a transmitter includes an encoding chain and a plurality of flip-flops. The encoding chain, including encoding units coupled in series, is configured to encode a plurality of symbols to generate a plurality of first wire states. The encoding units are arranged to receive the symbols respectively, and convert respective symbol values of the symbols to the first wire states respectively. A first encoding unit is configured to convert a symbol value of a corresponding symbol according to a second wire state provided by a second encoding unit. The flip-flops are arranged to receive and output the first wire states according to a clock signal, respectively. One of the flip-flops is coupled between the first encoding unit and the second encoding unit. The second wire state provided by the second encoding unit is sent to the first encoding unit through the one of the flip-flops.

    Integrated circuit having lanes interchangeable between clock and data lanes in clock forward interface receiver
    8.
    发明授权
    Integrated circuit having lanes interchangeable between clock and data lanes in clock forward interface receiver 有权

    公开(公告)号：US11609872B2

    公开(公告)日：2023-03-21

    申请号：US17343704

    申请日：2021-06-09

    申请人： M31 TECHNOLOGY CORPORATION

    发明人： Yueh-Chuan Lu ,  Ching-Hsiang Chang

    IPC分类号： G06F13/20 ,  G06F1/10

    摘要： An integrated circuit in a transmitter includes a multi-lane interface, N signal generating circuits, a lane selection circuit and a control circuit. The multi-lane interface has N lanes. M of the N signal generating circuits are configured to generate M clock signals respectively. (N-M) of the N signal generating circuits are configured to generate (N-M) data signals respectively. The lane selection circuit is configured to select M of the N lanes as M clock lanes by coupling the M clock signals to the M clock lanes respectively, and couple one of the (N-M) data signals to one of remaining (N-M) lanes, serving as (N-M) data lanes, according to a data select signal. The control circuit is configured to generate a data select signal according to a lane identifier of the one of the (N-M) lanes. The data select signal has a signal value mapping to the lane identifier.

    Integrated circuit having lanes interchangeable between clock and data lanes in clock forward interface receiver
    9.
    发明授权
    Integrated circuit having lanes interchangeable between clock and data lanes in clock forward interface receiver 有权

    公开(公告)号：US11055241B2

    公开(公告)日：2021-07-06

    申请号：US16529575

    申请日：2019-08-01

    申请人： M31 TECHNOLOGY CORPORATION

    发明人： Yueh-Chuan Lu ,  Ching-Hsiang Chang

    IPC分类号： G06F13/20 ,  G06F1/10

    摘要： An integrated circuit in a physical layer of a receiver is provided. The integrated circuit includes a multi-lane interface, a lane selection circuit and N sampling circuits. The multi-lane interface has N lanes. N is an integer greater than one. The lane selection circuit, coupled to the multi-lane interface, is configured to select M of the N lanes as M clock lanes, and output M signals on the M clock lanes respectively. M is a positive integer less than N. Remaining (N−M) lanes serve as (N−M) data lanes. The N sampling circuits are coupled to the multi-lane interface and the lane selection circuit. (N−M) of the N sampling circuits are coupled to the (N−M) data lanes respectively. Each of the (N−M) sampling circuits is configured to sample a signal on one of the (N−M) data lanes according to one of the M signals on the M clock lanes.

    ENCODING AND DECODING ARCHITECTURE FOR HIGH-SPEED DATA COMMUNICATION SYSTEM AND RELATED PHYSICAL LAYER CIRCUIT, TRANSMITTER AND RECEIVER AND COMMUNICATION SYSTEM THEREOF
    10.
    发明申请
    ENCODING AND DECODING ARCHITECTURE FOR HIGH-SPEED DATA COMMUNICATION SYSTEM AND RELATED PHYSICAL LAYER CIRCUIT, TRANSMITTER AND RECEIVER AND COMMUNICATION SYSTEM THEREOF 审中-公开

    公开(公告)号：US20190158127A1

    公开(公告)日：2019-05-23

    申请号：US15956709

    申请日：2018-04-18

    申请人： M31 Technology Corporation

    发明人： Yueh-Chuan Lu

    IPC分类号： H03M13/37 ,  H03M9/00 ,  H03M7/30

    摘要： The present invention proposes an inventive encoding and decoding architecture for use in a physical layer of a high-speed serial data communication system, such as, MIPI C-PHY. Embodiments of the present invention include encoding chains and decoding chains adaptable to physical layer circuits of transmitters and receivers, respectively. The physical layer circuit of a transmitter includes: an encoding chain and a parallel-to-serial (P2S) converter. The encoding chain having a plurality of encoding unit coupled in series, and is arranged to receive a plurality of first symbols and convert each of the symbols to a corresponding wire state, thereby to generate a plurality of wire states. The P2S converter is coupled to the encoding chain, arranged to receive the plurality of wire states and serialize the plurality of wire states to provide a sequence of wire states.