公开(公告)号：US20090035924A1

公开(公告)日：2009-02-05

申请号：US12037533

申请日：2008-02-26

Applicant: Thomas Feudel ,  Manfred Horstmann ,  Andreas Gehring

Inventor： Thomas Feudel ,  Manfred Horstmann ,  Andreas Gehring

IPC: H01L21/265

CPC classification number: H01L21/823418 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/324 ,  H01L21/82345 ,  H01L21/823814 ,  H01L21/823842 ,  H01L29/6659 ,  H01L29/7833

Abstract: A method of forming a semiconductor structure includes providing a substrate having a first feature and a second feature. A mask is formed over the substrate. The mask covers the first feature. An ion implantation process is performed to introduce ions of a non-doping element into the second feature. The mask is adapted to absorb ions impinging on the first feature. After the ion implantation process, an annealing process is performed.

Abstract translation: 形成半导体结构的方法包括提供具有第一特征和第二特征的基板。 在衬底上形成掩模。 面罩涵盖了第一个功能。 执行离子注入工艺以将非掺杂元素的离子引入到第二特征中。 掩模适于吸收撞击第一特征的离子。 在离子注入工艺之后，进行退火处理。

公开(公告)号：US20080182371A1

公开(公告)日：2008-07-31

申请号：US11778930

申请日：2007-07-17

Applicant: Andreas Gehring ,  Maciej Wiatr ,  Andy Wei ,  Thorsten Kammler ,  Roman Boschke ,  Casey Scott

Inventor： Andreas Gehring ,  Maciej Wiatr ,  Andy Wei ,  Thorsten Kammler ,  Roman Boschke ,  Casey Scott

IPC: H01L21/8238

CPC classification number: H01L29/6656 ,  H01L21/823807 ,  H01L29/1087 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/66636

Abstract: By providing a protection layer on a silicon/germanium material of high germanium concentration, a corresponding loss of strained semiconductor material may be significantly reduced or even completely avoided. The protection layer may be formed prior to critical cleaning processes and may be maintained until the formation of metal silicide regions. Hence, high performance gain of P-type transistors may be accomplished without requiring massive overfill during the selective epitaxial growth process.

Abstract translation: 通过在高锗浓度的硅/锗材料上提供保护层，相应的应变半导体材料的损失可以显着降低甚至完全避免。 保护层可以在关键的清洁过程之前形成，并且可以保持直到形成金属硅化物区域。 因此，可以在选择性外延生长工艺期间不需要大量过量填充来实现P型晶体管的高性能增益。

公开(公告)号：US20080001178A1

公开(公告)日：2008-01-03

申请号：US11674713

申请日：2007-02-14

Applicant: Andreas Gehring ,  Ralf Van Bentum ,  Markus Lenski

Inventor： Andreas Gehring ,  Ralf Van Bentum ,  Markus Lenski

IPC: H01L29/76 ,  H01L29/745

CPC classification number: H01L27/092 ,  H01L21/823412 ,  H01L21/82345 ,  H01L21/823807 ,  H01L21/823842 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/7845 ,  H01L29/7848

Abstract: By forming a stressed semiconductor material in a gate electrode, a biaxial tensile strain may be induced in the channel region, thereby significantly increasing the charge carrier mobility. This concept may be advantageously combined with additional strain-inducing sources, such as embedded strained semiconductor materials in the drain and source regions, thereby providing the potential for enhancing transistor performance without contributing to process complexity.

Abstract translation: 通过在栅电极中形成应力半导体材料，可以在沟道区域中诱发双轴拉伸应变，从而显着提高载流子迁移率。 该概念可以有利地与额外的应变诱发源（例如在漏极和源极区域中的嵌入式应变半导体材料）结合，从而提供增强晶体管性能的潜力，而不会造成工艺复杂性。

公开(公告)号：US08652913B2

公开(公告)日：2014-02-18

申请号：US11778930

申请日：2007-07-17

Applicant: Andreas Gehring ,  Maciej Wiatr ,  Andy Wei ,  Thorsten Kammler ,  Roman Boschke ,  Casey Scott

Inventor： Andreas Gehring ,  Maciej Wiatr ,  Andy Wei ,  Thorsten Kammler ,  Roman Boschke ,  Casey Scott

IPC: H01L21/336

CPC classification number: H01L29/6656 ,  H01L21/823807 ,  H01L29/1087 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/66636

Abstract: By providing a protection layer on a silicon/germanium material of high germanium concentration, a corresponding loss of strained semiconductor material may be significantly reduced or even completely avoided. The protection layer may be formed prior to critical cleaning processes and may be maintained until the formation of metal silicide regions. Hence, high performance gain of P-type transistors may be accomplished without requiring massive overfill during the selective epitaxial growth process.

Abstract translation: 通过在高锗浓度的硅/锗材料上提供保护层，相应的应变半导体材料的损失可以显着降低甚至完全避免。 保护层可以在关键的清洁过程之前形成，并且可以保持直到形成金属硅化物区域。 因此，可以在选择性外延生长工艺期间不需要大量过量填充来实现P型晶体管的高性能增益。

公开(公告)号：US08530894B2

公开(公告)日：2013-09-10

申请号：US13474934

申请日：2012-05-18

Applicant: Anthony Mowry ,  Casey Scott ,  Vassilios Papageorgiou ,  Andy Wei ,  Markus Lenski ,  Andreas Gehring

Inventor： Anthony Mowry ,  Casey Scott ,  Vassilios Papageorgiou ,  Andy Wei ,  Markus Lenski ,  Andreas Gehring

IPC: H01L21/00

CPC classification number: H01L29/7848 ,  H01L21/823807 ,  H01L21/823814 ,  H01L22/34 ,  H01L29/165 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7833

Abstract: By providing a test structure for evaluating the patterning process and/or the epitaxial growth process for forming embedded semiconductor alloys in sophisticated semiconductor devices, enhanced statistical relevance in combination with reduced test time may be accomplished.

Abstract translation: 通过提供用于评估用于在复杂半导体器件中形成嵌入式半导体合金的图案化工艺和/或外延生长工艺的测试结构，可以实现与减少的测试时间相结合的增强的统计相关性。

公开(公告)号：US08093634B2

公开(公告)日：2012-01-10

申请号：US12394475

申请日：2009-02-27

Applicant: Anthony Mowry ,  Andy Wei ,  Andreas Gehring ,  Casey Scott

Inventor： Anthony Mowry ,  Andy Wei ,  Andreas Gehring ,  Casey Scott

IPC: H01L25/07 ,  H01L21/363 ,  H01L21/336

CPC classification number: H01L29/0847 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/41758 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/66772 ,  H01L29/7833 ,  H01L29/7848 ,  H01L29/78612 ,  H01L29/78621

Abstract: By repeatedly applying a process sequence comprising an etch process and a selective epitaxial growth process during the formation of drain and source areas in a transistor device, highly complex dopant profiles may be generated on the basis of in situ doping. Further-more, a strain material may be provided while stress relaxation mechanisms may be reduced due to the absence of any implantation processes.

Abstract translation: 通过在形成晶体管器件中的漏极和源极区域期间重复地应用包括蚀刻工艺和选择性外延生长工艺的工艺顺序，可以基于原位掺杂产生高度复杂的掺杂剂分布。 此外，可以提供应变材料，同时由于不存在任何植入过程而可以减小应力松弛机制。

公开(公告)号：US20110183477A1

公开(公告)日：2011-07-28

申请号：US13081575

申请日：2011-04-07

Applicant: Andreas Gehring ,  Jan Hoentschel ,  Andy Wei

Inventor： Andreas Gehring ,  Jan Hoentschel ,  Andy Wei

IPC: H01L21/84

CPC classification number: H01L21/8221 ,  H01L21/823481 ,  H01L21/823835 ,  H01L21/84 ,  H01L27/0688 ,  H01L27/1203 ,  H01L27/1207 ,  H01L29/66128 ,  H01L29/8611

Abstract: A substrate diode for an SOI device is formed in accordance with an appropriately designed manufacturing flow, wherein transistor performance enhancing mechanisms may be implemented substantially without affecting the diode characteristics. In one aspect, respective openings for the substrate diode may be formed after the formation of a corresponding sidewall spacer structure used for defining the drain and source regions, thereby obtaining a significant lateral distribution of the dopants in the diode areas, which may therefore provide sufficient process margins during a subsequent silicidation sequence on the basis of a removal of the spacers in the transistor devices. In a further aspect, in addition to or alternatively, an offset spacer may be formed substantially without affecting the configuration of respective transistor devices.

Abstract translation: 根据适当设计的制造流程形成用于SOI器件的衬底二极管，其中可以基本上实现晶体管性能增强机制而不影响二极管特性。 在一个方面，用于衬底二极管的相应开口可以在形成用于限定漏极和源极区域的相应的侧壁间隔结构形成之后形成，从而获得掺杂剂在二极管区域中的显着的横向分布，这可能因此提供足够的 基于去除晶体管器件中的间隔物，在随后的硅化序列期间的工艺余量。 在另一方面，除了或者可选地，可以基本上形成偏移间隔物而不影响各个晶体管器件的配置。

公开(公告)号：US07897451B2

公开(公告)日：2011-03-01

申请号：US12123524

申请日：2008-05-20

Applicant: Maciej Wiatr ,  Casey Scott ,  Andreas Gehring ,  Peter Javorka ,  Andy Wei

Inventor： Maciej Wiatr ,  Casey Scott ,  Andreas Gehring ,  Peter Javorka ,  Andy Wei

IPC: H01L21/8238

CPC classification number: H01L21/823807 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/823814 ,  H01L29/1079 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/7843 ,  H01L29/7848

Abstract: By selectively applying a stress memorization technique to N-channel transistors, a significant improvement of transistor performance may be achieved. High selectivity in applying the stress memorization approach may be accomplished by substantially maintaining the crystalline state of the P-channel transistors while annealing the N-channel transistors in the presence of an appropriate material layer which may not to be patterned prior to the anneal process, thereby avoiding additional lithography and masking steps.

Abstract translation: 通过选择性地对N沟道晶体管施加应力记忆技术，可以实现晶体管性能的显着改善。 在施加应力记忆方法时的高选择性可以通过在存在可在退火工艺之前不被图案化的适当材料层的情况下退火N沟道晶体管的同时基本上保持P沟道晶体管的结晶状态来实现， 从而避免了额外的光刻和掩蔽步骤。

公开(公告)号：US07772077B2

公开(公告)日：2010-08-10

申请号：US11750816

申请日：2007-05-18

Applicant: Andreas Gehring ,  Andy Wei ,  Anthony Mowry ,  Manuj Rathor

Inventor： Andreas Gehring ,  Andy Wei ,  Anthony Mowry ,  Manuj Rathor

IPC: H01L21/336

CPC classification number: H01L29/7833 ,  H01L21/268 ,  H01L21/823807 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7843

Abstract: A method of forming a semiconductor structure comprises providing a semiconductor substrate comprising a first transistor element and a second transistor element. The first transistor element comprises at least one first amorphous region and the second transistor element comprises at least one second amorphous region. A stress-creating layer is formed over the first transistor element. The stress-creating layer does not cover the second transistor element. A first annealing process is performed. The first annealing process is adapted to re-crystallize the first amorphous region and the second amorphous region. After the first annealing process, a second annealing process is performed. The stress-creating layer remains on the semiconductor substrate during the second annealing process.

Abstract translation: 形成半导体结构的方法包括提供包括第一晶体管元件和第二晶体管元件的半导体衬底。 第一晶体管元件包括至少一个第一非晶区，而第二晶体管元件包括至少一个第二非晶区。 应力产生层形成在第一晶体管元件上。 应力产生层不覆盖第二晶体管元件。 执行第一退火处理。 第一退火工艺适于重新结晶第一非晶区域和第二非晶区域。 在第一退火处理之后，进行第二退火处理。 应力产生层在第二退火工艺期间保留在半导体衬底上。

公开(公告)号：US07763505B2

公开(公告)日：2010-07-27

申请号：US11740072

申请日：2007-04-25

Applicant: Andreas Gehring ,  Markus Lenski ,  Jan Hoentschel ,  Thorsten Kammler

Inventor： Andreas Gehring ,  Markus Lenski ,  Jan Hoentschel ,  Thorsten Kammler

IPC: H01L21/337

CPC classification number: H01L29/045 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/268 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7843

Abstract: By appropriately adapting the length direction and width directions of transistor devices with respect to the crystallographic orientation of the semiconductor material such that identical vertical and horizontal growth planes upon re-crystallizing amorphized portions are obtained, the number of corresponding stacking faults may be significantly reduced. Hence, transistor elements with extremely shallow PN junctions may be formed on the basis of pre-amorphization implantation processes while substantially avoiding any undue side effects typically obtained in conventional techniques due to stacking faults.

Abstract translation: 通过适当地适应晶体管器件的长度方向和宽度方向相对于半导体材料的晶体取向，使得在重新结晶非晶化部分时相同的垂直和水平生长面，可以显着地减少对应的堆垛层错的数量。 因此，具有非常浅的PN结的晶体管元件可以基于前非晶化注入工艺形成，同时基本上避免了由于堆垛层错而在常规技术中通常获得的任何不适当的副作用。