公开(公告)号：US07605740B2

公开(公告)日：2009-10-20

申请号：US12097040

申请日：2006-12-08

申请人： Marcel Pelgrom ,  Atul Katoch ,  Maarten Vertregt

发明人： Marcel Pelgrom ,  Atul Katoch ,  Maarten Vertregt

IPC分类号： H03M1/36

CPC分类号： H03M1/0673 ,  H03M1/365

摘要： A flash analog-to-digital converter comprises a resistive string powered by a reference voltage source for providing a set of equidistant reference voltages and a set of comparators for comparing the analog input signal with the reference voltages. A set of switches are arranged and controlled to perform an algorithm for mitigating the influence of mismatches between the components. The switches are arranged between the reference voltage source and the resistive string so that switches in the reference inputs to the comparators are avoided. The resistive string is preferably circular. The converter can handle differential signals.

摘要翻译： 闪存模数转换器包括由参考电压源供电的电阻串，用于提供一组等距参考电压，以及一组比较器，用于将模拟输入信号与参考电压进行比较。 一组开关被布置和控制以执行用于减轻组件之间的错配的影响的算法。 开关布置在参考电压源和电阻串之间，从而避免了比较器的参考输入中的开关。 电阻串优选为圆形。 转换器可以处理差分信号。

公开(公告)号：US20060244481A1

公开(公告)日：2006-11-02

申请号：US10558145

申请日：2004-05-17

申请人： Atul Katoch ,  Manish Garg ,  Evert Seevinck ,  Hendricus Veendrick

发明人： Atul Katoch ,  Manish Garg ,  Evert Seevinck ,  Hendricus Veendrick

IPC分类号： H03K19/003

CPC分类号： G06F13/4072

摘要： As technology scales, on-chip interconnects are becoming narrower, and the height of such interconnects is not scaling linearly with the width. This leads to an increase of coupling capacitance with neighboring wires, leading to higher crosstalk. It also leads to poor performance due to poor RC response at the receiving of the wire, which may even result in failure in very noisy environments. An adaptive threshold scheme is proposed in which receiver switching thresholds are adjusted according to the detected noise in bus lines. These noise levels are dependent on both the front-end processing (transistor performance) as well as on the backend processing (metal resistance, capacitance, width and spacing). The circuit therefore automatically compensates for process variations.

摘要翻译： 随着技术的发展，片上互连变得越来越窄，这种互连的高度并没有随宽度而线性缩放。 这导致与相邻导线的耦合电容的增加，导致更高的串扰。 由于在接收线路时RC响应差，导致性能差，甚至可能导致非常嘈杂的环境中的故障​​。 提出了一种自适应阈值方案，其中接收机切换阈值根据总线线路中检测到的噪声进行调整。 这些噪声水平取决于前端处理（晶体管性能）以及后端处理（金属电阻，电容，宽度和间距）。 因此，电路自动补偿过程变化。

公开(公告)号：US09324412B2

公开(公告)日：2016-04-26

申请号：US13791025

申请日：2013-03-08

申请人： Atul Katoch ,  Mayank Tayal

发明人： Atul Katoch ,  Mayank Tayal

IPC分类号： G11C7/22 ,  G11C11/419 ,  G11C7/08 ,  G11C7/12

CPC分类号： G11C11/419 ,  G11C7/08 ,  G11C7/12

摘要： A memory circuit includes a memory cell and a data circuit. In a write operation of the memory cell, the data circuit is configured to provide a first write logical value to the first output of the data circuit and to provide a second write logical value to the second output of the data circuit. The first write logical value is different from the second write logical value. In a read operation of the memory cell, the data circuit is configured to provide a same logical value to the first output and the second output of the data circuit.

摘要翻译： 存储电路包括存储单元和数据电路。 在存储单元的写入操作中，数据电路被配置为向数据电路的第一输出提供第一写入逻辑值，并向数据电路的第二输出提供第二写入逻辑值。 第一个写入逻辑值与第二个写入逻辑值不同。 在存储单元的读取操作中，数据电路被配置为向数据电路的第一输出和第二输出提供相同的逻辑值。

公开(公告)号：US09177631B2

公开(公告)日：2015-11-03

申请号：US12767979

申请日：2010-04-27

申请人： Atul Katoch

发明人： Atul Katoch

IPC分类号： G11C11/407 ,  G11C11/409 ,  G11C11/4076 ,  G11C11/4091 ,  G11C11/4094

CPC分类号： G11C7/062 ,  G11C11/4076 ,  G11C11/4091 ,  G11C11/4094

摘要： A memory circuit includes at least one first memory cell of a first memory array for storing a first datum. The at least one first memory cell is coupled with a first word line and a first bit line. A first bit line bar is disposed substantially parallel with the first bit line. A first switch is coupled between a sense amplifier and the first bit line bar. The first switch can electrically isolate the sense amplifier from the first bit line bar if the sense amplifier is capable of sensing a first voltage difference between the first bit line. The first bit line bar and the first voltage difference is substantially equal to or larger than a predetermined value.

摘要翻译： 存储器电路包括用于存储第一数据的第一存储器阵列的至少一个第一存储单元。 所述至少一个第一存储单元与第一字线和第一位线耦合。 第一位线条与第一位线基本平行地设置。 第一开关耦合在读出放大器和第一位线条之间。 如果读出放大器能够检测第一位线之间的第一电压差，则第一开关可以将读出放大器与第一位线条电隔离。 第一位线条和第一电压差基本上等于或大于预定值。

公开(公告)号：US08929160B2

公开(公告)日：2015-01-06

申请号：US13781159

申请日：2013-02-28

申请人： Atul Katoch ,  Mayank Tayal

发明人： Atul Katoch ,  Mayank Tayal

IPC分类号： G11C7/00 ,  G11C7/12 ,  G11C7/22

CPC分类号： G11C7/12 ,  G11C7/227 ,  G11C11/41 ,  G11C11/417 ,  G11C29/50012

摘要： A current flowing through a voltage line and/or a data line in a column of a tracking circuit is determined. A threshold tracking time delay of the tracking circuit is determined. Based on the determined current handled by the voltage line and/or the data line and the determined threshold tracking time delay, a plurality of columns in the tracking circuit, a number of first cells in each column of the plurality of columns, and a number of second cells in the each column of the plurality of columns are determined.

摘要翻译： 确定流过跟踪电路的列中的电压线和/或数据线的电流。 确定跟踪电路的阈值跟踪时间延迟。 基于由电压线和/或数据线处理的确定的电流和确定的阈值跟踪时间延迟，跟踪电路中的多个列，多个列的每列中的多个第一单元，以及数字 确定多个列的每列中的第二单元格。

公开(公告)号：US08675433B2

公开(公告)日：2014-03-18

申请号：US13053660

申请日：2011-03-22

申请人： Atul Katoch

发明人： Atul Katoch

IPC分类号： G11C7/00

CPC分类号： G11C11/4074 ,  G11C7/08 ,  G11C11/4091

摘要： A circuit comprises a first node, a second node, a sense amplifier, at least one first transistor, at least one second transistor, and one or a combination of a first control circuit and a second control circuit. The first control circuit is configured to generate a first control signal for at least one first gate of the at least one first transistor. The first control signal is capable of having a first voltage level lower than a first operational voltage. The second control circuit is configured to generate a second control signal for at least one second gate of the at least one second transistor. The second control signal is capable of having a second voltage level higher than a second operational voltage.

摘要翻译： 电路包括第一节点，第二节点，读出放大器，至少一个第一晶体管，至少一个第二晶体管以及第一控制电路和第二控制电路的一个或组合。 第一控制电路被配置为产生用于至少一个第一晶体管的至少一个第一栅极的第一控制信号。 第一控制信号能够具有低于第一操作电压的第一电压电平。 第二控制电路被配置为为至少一个第二晶体管的至少一个第二栅极产生第二控制信号。 第二控制信号能够具有高于第二操作电压的第二电压电平。

公开(公告)号：US08619483B2

公开(公告)日：2013-12-31

申请号：US12831385

申请日：2010-07-07

申请人： Atul Katoch ,  Cormac Michael O'Connell

发明人： Atul Katoch ,  Cormac Michael O'Connell

IPC分类号： G11C7/00

CPC分类号： G11C7/06 ,  G11C7/12 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4097

摘要： A memory circuit includes at least one memory cell for storing a charge representative of a datum. The memory cell is coupled with a word line and a bit line. A sense amplifier is coupled with the bit line. The sense amplifier is capable of precharging the bit line to a first voltage that is substantially equal to and higher than a threshold voltage (Vt) of a first transistor of the sense amplifier.

摘要翻译： 存储电路包括至少一个用于存储表示数据的电荷的存储单元。 存储单元与字线和位线耦合。 读出放大器与位线耦合。 读出放大器能够将位线预充电到基本上等于并高于读出放大器的第一晶体管的阈值电压（Vt）的第一电压。

公开(公告)号：US20130010561A1

公开(公告)日：2013-01-10

申请号：US13618646

申请日：2012-09-14

申请人： Atul KATOCH ,  Mayank TAYAL

发明人： Atul KATOCH ,  Mayank TAYAL

IPC分类号： G11C7/02 ,  H03F3/45

CPC分类号： G11C7/065 ,  G11C7/08

摘要： Embodiments of the invention are related to sense amplifiers. In an embodiment involving a sense amplifier used with a memory cell, signals BL, ZBL, SN and SP are pre-charged and equalized to a voltage reference, e.g., Vref, using an equalizing signal. A compensation signal, e.g., SAC, is applied to compensate for the mismatch between transistors in the sense amplifier. The word line WL is activated to connect the memory cell to a bit line, e.g., bit line ZBL. Because the memory cell shares the charge with the connected bit line ZBL, it causes a differential signal to be developed between bit lines BL and ZBL. When enough split between bit lines BL and ZBL is developed, signals SP and SAE are raised to VDD (while signal SN has been lowered to VSS) to turn on the sense amplifier and allow it to function as desire. Other embodiments and exemplary applications are also disclosed.

摘要翻译： 本发明的实施例涉及读出放大器。 在涉及与存储器单元一起使用的读出放大器的实施例中，使用均衡信号将信号BL，ZBL，SN和SP预充电并均衡到电压参考值，例如Vref。 施加补偿信号，例如SAC，以补偿读出放大器中的晶体管之间的失配。 字线WL被激活以将存储器单元连接到位线，例如位线ZBL。 由于存储单元与所连接的位线ZBL共享电荷，所以在位线BL和ZBL之间产生差分信号。 当位线BL和ZBL之间的足够的分割被开发时，信号SP和SAE升高到VDD（当信号SN已经降低到VSS时），以使得读出放大器接通，并使其能够按需要起作用。 还公开了其它实施例和示例性应用。

公开(公告)号：US20120275242A1

公开(公告)日：2012-11-01

申请号：US13543495

申请日：2012-07-06

申请人： Atul KATOCH ,  Cormac Michael O'CONNELL

发明人： Atul KATOCH ,  Cormac Michael O'CONNELL

IPC分类号： G11C5/14 ,  G11C7/06

CPC分类号： G11C11/4091 ,  Y10T307/50

摘要： Some embodiments regard a circuit comprising a memory cell, a first data line, a second data line, a sensing circuit coupled to the first data line and the second data line, a node selectively coupled to at least three voltage sources via at least three respective switches, a fourth switch, and a fifth switch. A first voltage source is configured to supply a retention voltage to the node via a first switch. A second voltage source is configured to supply a ground reference voltage to the node via a second switch, and a third voltage source is configured to supply a reference voltage to the node via a third switch. The fourth switch and fifth switch are configured to receive a respective first control signal and second control signal and to pass a voltage at the node to the respective first data line and second data line.

摘要翻译： 一些实施例涉及包括存储器单元，第一数据线，第二数据线，耦合到第一数据线和第二数据线的感测电路的电路，经由至少三个相应的选择性地耦合到至少三个电压源的节点 开关，第四开关和第五开关。 第一电压源被配置为经由第一开关向节点提供保持电压。 第二电压源被配置为经由第二开关向节点提供接地参考电压，并且第三电压源被配置为经由第三开关向节点提供参考电压。 第四开关和第五开关被配置为接收相应的第一控制信号和第二控制信号，并将节点处的电压传递到相应的第一数据线和第二数据线。

公开(公告)号：US08238141B2

公开(公告)日：2012-08-07

申请号：US12852638

申请日：2010-08-09

申请人： Atul Katoch ,  Cormac Michael O'Connell

发明人： Atul Katoch ,  Cormac Michael O'Connell

IPC分类号： G11C11/24 ,  G11C7/00 ,  G11C5/14

CPC分类号： G11C11/4091 ,  Y10T307/50

摘要： Some embodiments regard a circuit comprising a memory cell, a first data line, a second data line, a sensing circuit coupled to the first data line and the second data line, a node selectively coupled to at least three voltage sources via at least three respective switches, a fourth switch, and a fifth switch. A first voltage source is configured to supply a retention voltage to the node via a first switch. A second voltage source is configured to supply a ground reference voltage to the node via a second switch, and a third voltage source is configured to supply a reference voltage to the node via a third switch. The fourth switch and fifth switch are configured to receive a respective first control signal and second control signal and to pass a voltage at the node to the respective first data line and second data line.

摘要翻译： 一些实施例涉及包括存储器单元，第一数据线，第二数据线，耦合到第一数据线和第二数据线的感测电路的电路，经由至少三个相应的选择性地耦合到至少三个电压源的节点 开关，第四开关和第五开关。 第一电压源被配置为经由第一开关向节点提供保持电压。 第二电压源被配置为经由第二开关向节点提供接地参考电压，并且第三电压源被配置为经由第三开关向节点提供参考电压。 第四开关和第五开关被配置为接收相应的第一控制信号和第二控制信号，并将节点处的电压传递到相应的第一数据线和第二数据线。