公开(公告)号：US20090058184A1

公开(公告)日：2009-03-05

申请号：US12231503

申请日：2008-09-02

Applicant: Ching-Chung Lin

Inventor： Ching-Chung Lin

IPC: H02M3/22

CPC classification number: H02M3/33523 ,  Y10T307/406 ,  Y10T307/505

Abstract: An power supply circuit includes at least one voltage converting circuit, a plurality of output branches, and a plurality of power assigning elements. The at least one voltage converting circuit is configured for converting a primary voltage signal to at least one alternating current (AC) voltage signal. Each of the output branches is configured for providing a direct current (DC) power supply to a respective load circuit based on the at least one AC voltage signal. The power assigning elements are configured to reassign the DC power supplies provided by the output branches to the load circuits.

Abstract translation: 电源电路包括至少一个电压转换电路，多个输出分支和多个功率分配元件。 所述至少一个电压转换电路被配置为将初级电压信号转换成至少一个交流（AC）电压信号。 每个输出分支被配置为基于至少一个AC电压信号向相应的负载电路提供直流（DC）电源。 功率分配元件被配置为将由输出分支提供的直流电源重新分配给负载电路。

公开(公告)号：US07355903B2

公开(公告)日：2008-04-08

申请号：US11181983

申请日：2005-07-15

Applicant: Chun-Hsiung Hung ,  Chuan-Ying Yu ,  Han-Sung Chen ,  Nai-Ping Kuo ,  Ching-Chung Lin ,  Kuen-Long Chang

Inventor： Chun-Hsiung Hung ,  Chuan-Ying Yu ,  Han-Sung Chen ,  Nai-Ping Kuo ,  Ching-Chung Lin ,  Kuen-Long Chang

IPC: G11C7/10

CPC classification number: G11C16/24

Abstract: A semiconductor device, including a memory cell having a control gate, a source and drain; and a current limiting circuit coupled to the source. The current limiting circuit may be configured to limit a current between the drain and source to not exceed a predetermined value; the current being generated in response to application of first and second voltages to the control gate and drain, respectively. The current limiting circuit may include a transistor comprising a first terminal, a second terminal, and a third terminal, wherein the first terminal may include a source of the transistor, the third terminal may include a drain of the transistor, and the second terminal may include a gate of the transistor, and wherein a stable bias may be applied to the second terminal of the transistor.

Abstract translation: 一种半导体器件，包括具有控制栅极，源极和漏极的存储单元; 以及耦合到源极的限流电路。 电流限制电路可以被配置为将漏极和源极之间的电流限制为不超过预定值; 响应于分别向控制栅极和漏极施加第一和第二电压而产生电流。 电流限制电路可以包括包括第一端子，第二端子和第三端子的晶体管，其中第一端子可以包括晶体管的源极，第三端子可以包括晶体管的漏极，并且第二端子可以 包括晶体管的栅极，并且其中可以将稳定的偏压施加到晶体管的第二端子。

公开(公告)号：US07315482B2

公开(公告)日：2008-01-01

申请号：US11250005

申请日：2005-10-13

Applicant: Ching Chung Lin ,  Nai Ping Kuo ,  Han Sung Chen

Inventor： Ching Chung Lin ,  Nai Ping Kuo ,  Han Sung Chen

IPC: G11C7/02

CPC classification number: G11C7/14 ,  G11C7/062 ,  G11C7/067 ,  G11C16/28

Abstract: In accordance with one embodiment of the invention, a memory device comprises an array of memory cells arranged into word lines and bit lines, with a sense amplifier and a plurality of reference cells for each bit line. The sense amplifier for a bit line compares the output of a memory cell for that bit line with the output of one of the plurality of reference cells for that bit line.

Abstract translation: 根据本发明的一个实施例，存储器件包括布置成字线和位线的存储器单元的阵列，具有读出放大器和用于每个位线的多个参考单元。 用于位线的读出放大器将该位线的存储器单元的输出与该位线的多个参考单元之一的输出进行比较。

公开(公告)号：US07236404B2

公开(公告)日：2007-06-26

申请号：US11210425

申请日：2005-08-24

Applicant: Ching Chung Lin ,  Ken Hui Chen ,  Nai Ping Kuo ,  Han Sung Chen ,  Chun Hsiung Hung ,  Wen Yi Hsieh

Inventor： Ching Chung Lin ,  Ken Hui Chen ,  Nai Ping Kuo ,  Han Sung Chen ,  Chun Hsiung Hung ,  Wen Yi Hsieh

IPC: G11C11/34

CPC classification number: G11C16/0491 ,  G11C16/0475 ,  G11C16/14

Abstract: A virtual ground NROM array has a matrix of NROM cells in which during an erase operation the non-erasing side of NROM cells are connected to a common node for enhancing the erase uniformity of the NROM array. If an operation requests erasing on the left side of NROM cells, a positive voltage is supplied from an internal power supply to the left side for each of the NROM cells, and the right side for each of the NROM cells is discharged to a common node. If an operation requests erasing the right side of NROM cells, a positive voltage is supplied from the internal power supply to the right side for each of the NROM cells, and the right side for each of the NROM cells is connected to the common node. The voltage level of the common mode is selected to be sufficiently high in order to prevent from punch through while at the same time sufficiently low to maintain the lateral electric field for erase operation to function optimally. In an alternative embodiment, non-erasing sides of NROM cells in the NROM array are connected to a current source during an erase operation for enhancing the erase uniformity of the NROM array. If an operation requests erasing the left side of NROM cells, a positive voltage is supplied from an internal power supply to the left side for each of the NROM cells, and the right side for each of the NROM cells is discharged to a current source. If an operation requests erasing the right side of NROM cells, a positive voltage is supplied from the internal power supply to the right side for each of the NROM cells, and the right side for each of the NROM cells is connected to the current source.

公开(公告)号：US20060268642A1

公开(公告)日：2006-11-30

申请号：US11137503

申请日：2005-05-26

Applicant: Han-Sung Chen ,  Chia-Yen Yeh ,  Chen-Hao Po ,  Ching-Chung Lin

Inventor： Han-Sung Chen ,  Chia-Yen Yeh ,  Chen-Hao Po ,  Ching-Chung Lin

IPC: G11C7/00

CPC classification number: G11C7/1075 ,  G11C5/066

Abstract: A serial peripheral flash memory device uses a plurality of dummy input/output terminals to enable the selection of a parallel mode for devices that have a slower serial clock speed. In parallel mode, data is transmitted over the plurality of dummy input/output terminals to allow a plurality of bits to be transmitted at the same time improving the data transmission rate at the slower serial clock speed.

Abstract translation: 串行外围闪存器件使用多个虚拟输入/输出端子，以便能够对具有较慢串行时钟速度的器件选择并行模式。 在并行模式下，通过多个虚拟输入/输出端子发送数据，以允许同时发送多个位，以较慢的串行时钟速度提高数据传输速率。

公开(公告)号：US20060109674A1

公开(公告)日：2006-05-25

申请号：US11138453

申请日：2005-05-27

Applicant: Der-Woei Hsaio ,  Bor-Jyh Pan ,  Ching-Chung Lin

Inventor： Der-Woei Hsaio ,  Bor-Jyh Pan ,  Ching-Chung Lin

IPC: F21V15/04

CPC classification number: G02F1/133608 ,  F21V15/04 ,  G02F1/133604 ,  G02F2001/133612 ,  H01J61/305

Abstract: The present invention relates to a backlight module, wherein by disposing buffer elements in the edges and/or below the plate lamp, the plate lamp of the backlight module can avoid the damage resulting from an external force. In addition to a vibration-resistant effect, the buffer elements disposed below the bottom of the plate lamp can further maintain a uniform spacing between the plate lamp and the rear frame so that the light-emitting efficiency, brightness uniformity, and operation can be maintained.

Abstract translation: 背光模组技术领域本发明涉及一种背光模组，其特征在于，通过在所述平板灯的边缘和/或下方设置缓冲元件，所述背光模块的所述板灯可以避免由外力引起的损坏。 除了防振效果之外，设置在板灯底部下方的缓冲元件还可以保持板灯与后框架之间的均匀间隔，从而可以保持发光效率，亮度均匀性和操作 。

公开(公告)号：US20060007734A1

公开(公告)日：2006-01-12

申请号：US10886076

申请日：2004-07-06

Applicant: Ching-chung Lin ,  Nai-ping Kuo ,  Han-sung Chen

Inventor： Ching-chung Lin ,  Nai-ping Kuo ,  Han-sung Chen

IPC: G11C11/34

CPC classification number: G11C16/3468

Abstract: A nitride read only memory (NROM) erase system is disclosed. The NROM erase system comprises at least one memory sector, N sense amplifiers, and N buffers. The memory sector is segmented into N erase retry units according to the number of the sense amplifiers. One buffer corresponds with one erase retry unit and one sense amplifier. The N buffers are used to indicate whether their corresponding erase retry units are erased after an erase process of an erase operation. One of the buffers will be set if its corresponding erase retry unit is not erased. In this case, a subsequent erase process will begin to erase the un-erased erase retry unit. The erase retry units that are erased in a previous erase process will not be affected by the subsequent erase process. A method for using the disclosed NROM erase system is also described.

Abstract translation: 公开了一种氮化物只读存储器（NROM）擦除系统。 NROM擦除系统包括至少一个存储器扇区，N个读出放大器和N个缓冲器。 根据感测放大器的数量，存储器扇区被分割成N个擦除重试单元。 一个缓冲器对应于一个擦除重试单元和一个读出放大器。 N个缓冲器用于指示在擦除操作的擦除处理之后它们相应的擦除重试单元是否被擦除。 如果其相应的擦除重试单元未被擦除，其中一个缓冲区将被设置。 在这种情况下，随后的擦除过程将开始擦除未擦除的擦除重试单元。 在以前的擦除过程中擦除的擦除重试单元不会受到后续擦除过程的影响。 还描述了使用所公开的NROM擦除系统的方法。

公开(公告)号：US08300371B2

公开(公告)日：2012-10-30

申请号：US12763152

申请日：2010-04-19

Applicant: Xian-Jun Su ,  Ching-Chung Lin

Inventor： Xian-Jun Su ,  Ching-Chung Lin

IPC: H02H9/00

CPC classification number: G02F1/136204

Abstract: An electrostatic discharge protection circuit includes an input terminal, a first diode, a second diode, a third diode, a fourth diode, a plurality of voltage stabilizer circuits, and a power terminal. The input terminal and the cathode of the second diode connect to the anode of the first diode; the voltage stabilizer circuits connect in parallel between the cathode of the first diode and the anode of the second diode. The power terminal connects to the anode of the third diode, the cathode of the third diode connects to the cathode of the first diode. The cathode of the fourth diode connects to ground, the anode of the fourth diode connects to the anode of the second diode.

Abstract translation: 静电放电保护电路包括输入端子，第一二极管，第二二极管，第三二极管，第四二极管，多个稳压电路和电源端子。 第二二极管的输入端子和阴极连接到第一二极管的阳极; 电压稳定器电路并联连接在第一二极管的阴极和第二二极管的阳极之间。 电源端子连接到第三个二极管的阳极，第三个二极管的阴极连接到第一个二极管的阴极。 第四二极管的阴极连接到地，第四二极管的阳极连接到第二二极管的阳极。

公开(公告)号：US08094493B2

公开(公告)日：2012-01-10

申请号：US11271300

申请日：2005-11-10

Applicant: Wen-Yi Hsieh ,  Ken-Hui Chen ,  Chun-Hsiung Hung ,  Han-Sung Chen ,  Nai-Ping Kuo ,  Ching-Chung Lin ,  Chuan-Ying Yu

Inventor： Wen-Yi Hsieh ,  Ken-Hui Chen ,  Chun-Hsiung Hung ,  Han-Sung Chen ,  Nai-Ping Kuo ,  Ching-Chung Lin ,  Chuan-Ying Yu

IPC: G11C11/34 ,  G11C7/02

CPC classification number: G11C16/28 ,  G11C16/04 ,  G11C16/0475 ,  G11C29/028 ,  G11C29/24 ,  G11C29/50004 ,  G11C2211/5634

Abstract: A memory device is disclosed that includes a plurality of word lines and a plurality of memory cells operating in one of a plurality of modes and coupled to at least one of the word lines. The memory device also includes a plurality of reference lines and reference cells. Each reference cell corresponds to one of the operating modes, supplies a reference current for the corresponding mode, and is coupled to at least one of the reference lines. A reference cell current from a reference cell can also be compared to a target range and, if outside the target range, the voltage level on a corresponding reference line can be adjusted accordingly such that the reference current falls within the target range (i.e., reference current trimming).

Abstract translation: 公开了一种存储器件，其包括多个字线和以多个模式之一工作并耦合到至少一个字线的多个存储单元。 存储装置还包括多个参考线和参考单元。 每个参考单元对应于一个操作模式，为相应模式提供参考电流，并耦合到至少一个参考线。 来自参考单元的参考单元电流也可以与目标范围进行比较，并且如果在目标范围之外，可以相应地调整相应参考线上的电压电平，使得参考电流落在目标范围内（即，参考 当前修剪）。

公开(公告)号：US20110110121A1

公开(公告)日：2011-05-12

申请号：US12890691

申请日：2010-09-26

Applicant: HE-KANG ZHOU ,  CHING-CHUNG LIN

Inventor： HE-KANG ZHOU ,  CHING-CHUNG LIN

IPC: H02M3/335

CPC classification number: H02M1/36 ,  H02M3/33507 ,  H02M2001/0048 ,  Y02B70/1491

Abstract: A power supply circuit includes a rectifying circuit, at least one filter member, a transformer, and a control circuit. The rectifying circuit is configured to receive a primary AC voltage signal and convert the primary AC voltage signal to a DC voltage signal. The at least one filter member is grounded via a current-limiting module, and is configured to filter the DC voltage signal. The transformer is configured to transform the filtered DC voltage signal to a main power voltage signal, and output the main power voltage signal. The control circuit is configured to enable the current-limiting element to function when the power supply circuit is powered on, and disable the current-limiting element when the power supply circuit is in a normal working state.

Abstract translation: 电源电路包括整流电路，至少一个滤波器构件，变压器和控制电路。 整流电路被配置为接收主交流电压信号并将初级交流电压信号转换成直流电压信号。 至少一个滤波器构件通过限流模块接地，并且被配置为对直流电压信号进行滤波。 变压器被配置为将滤波的直流电压信号转换成主电源电压信号，并输出主电源电压信号。 控制电路被配置为当电源电路通电时使限流元件起作用，并且当电源电路处于正常工作状态时禁止限流元件。