公开(公告)号：US07117284B2

公开(公告)日：2006-10-03

申请号：US10714562

申请日：2003-11-17

申请人： Simon Charles Watt ,  Christopher Bentley Dornan ,  Luc Orion ,  Nicolas Chaussade ,  Lionel Belnet ,  Stephane Eric Sebastien Brochier ,  David Hennah Mansell ,  Jonathan Sean Callan

发明人： Simon Charles Watt ,  Christopher Bentley Dornan ,  Luc Orion ,  Nicolas Chaussade ,  Lionel Belnet ,  Stephane Eric Sebastien Brochier ,  David Hennah Mansell ,  Jonathan Sean Callan

IPC分类号： G06F13/24

CPC分类号： G06F9/4812

摘要： A data processing apparatus is operable in a plurality of modes and in either a secure domain or a non-secure domain. When operating in a secure mode within the secure domain a program has access to secure data which is not accessible when the processor is operating in a non-secure mode. A vectored interrupt controller is provided to generate an exception handler address in response to an occurrence of an except condition. The vectored interrupt controller is programmable with parameters specifying for each exception condition whether an exception handler in the secure or the non-secure domain should be triggered and an exception handler address for use if the exception occurs when in the appropriate domain. The vectored interrupt controller also includes a parameter specifying a domain switching exception handler address for use if the exception condition occurs when the processor is not in the appropriate domain.

摘要翻译： 数据处理装置可以以多种模式操作，也可以在安全域或非安全域中操作。 当在安全域内以安全模式操作时，程序可以访问当处理器以非安全模式操作时无法访问的安全数据。 提供向量中断控制器以响应于发生除了条件而产生异常处理程序地址。 向量中断控制器是可编程的，参数指定每个异常情况是否应触发安全或非安全域中的异常处理程序，如果在适当的域中发生异常，则使用异常处理程序地址。 向量中断控制器还包括指定域切换异常处理程序地址的参数，以便在处理器不在适当域中时发生异常情况时使用。

公开(公告)号：US09158574B2

公开(公告)日：2015-10-13

申请号：US13299403

申请日：2011-11-18

申请人： David Hennah Mansell ,  Timothy Holroyd Glauert

发明人： David Hennah Mansell ,  Timothy Holroyd Glauert ,  Michael Robert Nonweiler

IPC分类号： G06F9/48 ,  G06F11/36

CPC分类号： G06F9/4812 ,  G06F9/4806 ,  G06F11/3636 ,  G06F11/3656 ,  G06F11/3664

摘要： A method and apparatus for processing data when an interrupt is received during processing of a function at a point during the processing at which a portion of the function has been processed then a control parameter is accessed. In response to a control parameter having a value indicting that the function has idempotence, processing of the function is stopped, and information on progress of the function is discarded such that following completion of the interrupt the portion of the function that has already been processed is processed again. In response to the control parameter having a value indicating that the function does not have idempotence, processing of the function is suspended without discarding information on progress of the function that has already been processed such that following completion of the interrupt the processing is resumed from a point that it reached when it was suspended.

摘要翻译： 一种处理数据的方法和装置，用于在处理功能的处理期间处理功能期间接收到中断时，处理该功能的一部分，然后控制参数被访问。 响应于具有指示该功能具有等效性的值的控制参数，功能的处理被停止，并且丢弃关于该功能的进度的信息，使得在中断完成之后，已经处理的功能的部分是 再次处理 响应于具有指示该功能不具有幂等值的值的控制参数，暂停功能的处理，而不丢弃关于已经被处理的功能的进展的信息，使得在完成中断之后，从 指出它暂停时达到。

公开(公告)号：US08140820B2

公开(公告)日：2012-03-20

申请号：US12153617

申请日：2008-05-21

申请人： David Hennah Mansell ,  Richard Roy Grisenthwaite

发明人： David Hennah Mansell ,  Richard Roy Grisenthwaite

IPC分类号： G06F12/10

CPC分类号： G06F12/1009 ,  G06F12/1036

摘要： A data processing apparatus has address translation circuitry which is responsive to an access request specifying a virtual address, to perform a multi-stage address translation process to produce, via at least one intermediate address, a physical address in memory corresponding to the virtual address. The address translation circuitry references a storage unit, with each entry of the storage unit storing address translation information for one or more virtual addresses. Each entry has a field indicating whether the address translation information is consolidated address translation information or partial address translation information. If when processing an access request, it is determined that the relevant entry in the storage unit provides consolidated address translation information, the address translation circuitry produces a physical address directly from the consolidated address translation information. If on the other hand the relevant entry stores partial address translation information, the address translation circuitry produces an intermediate address from the partial address translation information and then performs the remainder of the multi-stage address translation process. Such an approach provides the performance benefits associated with a consolidated entry mechanism within the storage unit, while also allowing certain problem cases to be handled correctly and in an efficient manner.

摘要翻译： 数据处理装置具有响应于指定虚拟地址的访问请求的地址转换电路，以执行多级地址转换处理，以通过至少一个中间地址产生与虚拟地址相对应的存储器中的物理地址。 地址转换电路参考存储单元，存储单元的每个条目存储一个或多个虚拟地址的地址转换信息。 每个条目具有指示地址转换信息是合并地址转换信息还是部分地址转换信息的字段。 如果当处理访问请求时，确定存储单元中的相关条目提供合并的地址转换信息，地址转换电路直接从合并地址转换信息产生物理地址。 如果相关条目存储部分地址转换信息，则地址转换电路从部分地址转换信息产生中间地址，然后执行多级地址转换处理的剩余部分。 这种方法提供了与存储单元内的综合进入机制相关联的性能优点，同时还允许以有效的方式正确地处理某些问题情况。

公开(公告)号：US08086829B2

公开(公告)日：2011-12-27

申请号：US12379970

申请日：2009-03-05

申请人： Luc Orion ,  David Hennah Mansell ,  Michael Robert Nonweiler

发明人： Luc Orion ,  David Hennah Mansell ,  Michael Robert Nonweiler

IPC分类号： G06F9/00

CPC分类号： G06F9/4812 ,  G06F11/3636 ,  G06F11/3656 ,  G06F11/3664

摘要： A method of processing data comprising: processing a function using a processor operable to perform a plurality of functions, the processor having interrupts enabled; receiving an interrupt at the processor; suspending processing of the function; accessing at least one control parameter, the at least one control parameter indicating whether processing of the function should be resumed from the point where it was interrupted or whether the function should be repeated following the interrupt; following completion of the interrupt continuing processing of the function either at a start of the function or at a point at which it was interrupted dependent upon the control parameter. A function being an application, a thread, a system software routine, or multiple processing steps defined by software.

摘要翻译： 一种处理数据的方法，包括：使用可执行多个功能的处理器处理功能，所述处理器具有使能的中断; 在处理器处接收中断; 暂停处理功能; 访问至少一个控制参数，所述至少一个控制参数指示是否应该从其被中断的点恢复该功能的处理，或者该中断之后应该重复该功能; 在完成功能开始的中断继续处理之后，或者根据控制参数中断处理中断点。 作为应用程序，线程，系统软件程序或由软件定义的多个处理步骤的功能。

公开(公告)号：US20090292899A1

公开(公告)日：2009-11-26

申请号：US12153617

申请日：2008-05-21

申请人： David Hennah MANSELL ,  Richard Roy GRISENTHWAITE

发明人： David Hennah MANSELL ,  Richard Roy GRISENTHWAITE

IPC分类号： G06F12/10

CPC分类号： G06F12/1009 ,  G06F12/1036

摘要： A data processing apparatus has address translation circuitry which is responsive to an access request specifying a virtual address, to perform a multi-stage address translation process to produce, via at least one intermediate address, a physical address in memory corresponding to the virtual address. The address translation circuitry references a storage unit, with each entry of the storage unit storing address translation information for one or more virtual addresses. Each entry has a field indicating whether the address translation information is consolidated address translation information or partial address translation information. If when processing an access request, it is determined that the relevant entry in the storage unit provides consolidated address translation information, the address translation circuitry produces a physical address directly from the consolidated address translation information. If on the other hand the relevant entry stores partial address translation information, the address translation circuitry produces an intermediate address from the partial address translation information and then performs the remainder of the multi-stage address translation process. Such an approach provides the performance benefits associated with a consolidated entry mechanism within the storage unit, whilst also allowing certain problem cases to be handled correctly and in an efficient manner.

摘要翻译： 数据处理装置具有响应于指定虚拟地址的访问请求的地址转换电路，以执行多级地址转换处理，以通过至少一个中间地址产生与虚拟地址相对应的存储器中的物理地址。 地址转换电路参考存储单元，存储单元的每个条目存储一个或多个虚拟地址的地址转换信息。 每个条目具有指示地址转换信息是合并地址转换信息还是部分地址转换信息的字段。 如果当处理访问请求时，确定存储单元中的相关条目提供合并的地址转换信息，地址转换电路直接从合并地址转换信息产生物理地址。 如果相关条目存储部分地址转换信息，则地址转换电路从部分地址转换信息产生中间地址，然后执行多级地址转换处理的剩余部分。 这种方法提供了与存储单元内的综合进入机制相关联的性能优点，同时还允许以正确和有效的方式处理某些问题情况。

公开(公告)号：US07539853B2

公开(公告)日：2009-05-26

申请号：US10713456

申请日：2003-11-17

申请人： Luc Orion ,  David Hennah Mansell ,  Michael Robert Nonweiler

发明人： Luc Orion ,  David Hennah Mansell ,  Michael Robert Nonweiler

IPC分类号： G06F9/00

CPC分类号： G06F9/4812 ,  G06F11/3636 ,  G06F11/3656 ,  G06F11/3664

摘要： A method of processing data comprising: processing a function using a processor operable to perform a plurality of functions, the processor having interrupts enabled; receiving an interrupt at the processor; suspending processing of the function; accessing at least one control parameter, the at least one control parameter indicating whether processing of the function should be resumed from the point where it was interrupted or whether the function should be repeated following the interrupt; following completion of the interrupt continuing processing of the function either at a start of the function or at a point at which it was interrupted dependent upon the control parameter. A function being an application, a thread, a system software routine, or multiple processing steps defined by software.

摘要翻译： 一种处理数据的方法，包括：使用可执行多个功能的处理器处理功能，所述处理器具有使能的中断; 在处理器处接收中断; 暂停处理功能; 访问至少一个控制参数，所述至少一个控制参数指示是否应该从其被中断的点恢复该功能的处理，或者该中断之后应该重复该功能; 在完成功能开始的中断继续处理之后，或者根据控制参数中断处理中断点。 作为应用程序，线程，系统软件程序或由软件定义的多个处理步骤的功能。

公开(公告)号：US07506091B2

公开(公告)日：2009-03-17

申请号：US11603091

申请日：2006-11-22

申请人： Daniel Kershaw ,  Richard Roy Grisenthwaite ,  Stuart David Biles ,  David Hennah Mansell

发明人： Daniel Kershaw ,  Richard Roy Grisenthwaite ,  Stuart David Biles ,  David Hennah Mansell

IPC分类号： G06F13/26 ,  G06F13/24 ,  G06F13/32

CPC分类号： G06F21/52 ,  G06F13/26

摘要： An interrupt controller 2 is provided with priority registers 6 storing priority values P0-P9 used to determine prioritisation between received interrupt signals I0-I9. A priority value accessing circuit 10 provides multiple mappings to the priority values stored in dependence upon the priority value manager 16, 18, seeking to make an access. In this way, a first priority value manager 18, such as a secure operating system, can be given exclusive access to the highest priority values whilst a second priority value manager 16, such as a non-secure operating system, can be given access to a range of priority values as stored which are of a lower priority and yet as written or read by the non-secure operating system appear to the non-secure operating system to have a different, such as higher, priority level.

摘要翻译： 中断控制器2设置有优先级寄存器6，优先级寄存器6存储用于确定接收的中断信号I0-I9之间的优先级的优先权值P0-P9。 优先级值访问电路10根据优先权值管理器16,18存储的优先权值提供多个映射，寻求进行访问。 以这种方式，诸如安全操作系统的第一优先级值管理器18可以被授予对最高优先级值的排他访问，而可以给予诸如非安全操作系统的第二优先级值管理器16访问 所存储的优先级较低的范围的优先权较低，但由非安全操作系统写入或读取，对于非安全操作系统来说，具有不同的，例如较高的优先级。

公开(公告)号：US20090019256A1

公开(公告)日：2009-01-15

申请号：US12213147

申请日：2008-06-16

申请人： Katherine Elizabeth Kneebone ,  David Hennah Mansell

发明人： Katherine Elizabeth Kneebone ,  David Hennah Mansell

IPC分类号： G06F12/06

CPC分类号： G06F12/10

摘要： A data processing apparatus is provided comprising a memory, memory management unit and identification circuitry for identifying a predetermined type of data access transaction within a plurality of received data access transactions. The memory management unit is responsive to the predetermined type of data access transaction to both permit completion of a data access and to cause an exception to be raised despite completion of the data access having been permitted.

摘要翻译： 提供了一种数据处理装置，包括存储器，存储器管理单元和识别电路，用于在多个接收的数据访问事务中识别预定类型的数据访问事务。 存储器管理单元响应于预定类型的数据访问事务，以允许完成数据访问，并且在数据访问已被允许完成时引起异常。

公开(公告)号：US20080046701A1

公开(公告)日：2008-02-21

申请号：US11504780

申请日：2006-08-16

申请人： Daniel Kershaw ,  James Ian McNiven ,  Daniel Luke Kefford ,  David Hennah Mansell

发明人： Daniel Kershaw ,  James Ian McNiven ,  Daniel Luke Kefford ,  David Hennah Mansell

IPC分类号： G06F9/44

CPC分类号： G06F9/45533 ,  G06F9/30101 ,  G06F9/30181 ,  G06F9/30189 ,  G06F9/462 ,  G06F9/468 ,  G06F9/4812 ,  G06F21/74

摘要： A data processing apparatus and method are provided for controlling access to registers. The data processing apparatus comprises a processing unit for performing data processing operations on data values, the processing unit having a plurality of modes of operation. A plurality of registers are provided for storing data values for access by the processing unit, with a subset of those registers being mode specific registers. Each mode specific register is used by the processing unit when operating in an associated mode of operation. The processing unit is switchable between a plurality of contexts, the data values stored in the plurality of registers being dependent on a current context of the processing unit. The processing unit performs a switch operation to switch from the current context to a new context, during which the data values in the registers are updated having regard to the new context. A control register is provided which, for at least one mode of operation having at least one mode specific register associated therewith, has an access field which is programmable by the processing unit when operating in a predetermined mode of operation. When the access field is set, the processing unit is selectively denied access to the associated at least one mode specific register, whereby updating of the data values in the associated at least one mode specific register is avoided during the switch operation. This significantly increases the speed of the switch operation.

摘要翻译： 提供了一种用于控制对寄存器的访问的数据处理装置和方法。 数据处理装置包括用于对数据值执行数据处理操作的处理单元，所述处理单元具有多种操作模式。 提供多个寄存器用于存储用于由处理单元访问的数据值，其中这些寄存器的子集是模式特定寄存器。 当在相关联的操作模式下操作时，处理单元使用每个模式特定寄存器。 处理单元可在多个上下文之间切换，存储在多个寄存器中的数据值取决于处理单元的当前上下文。 处理单元执行切换操作以从当前上下文切换到新的上下文，在此期间，考虑到新的上下文，更新寄存器中的数据值。 提供控制寄存器，对于具有与其相关联的至少一个模式特定寄存器的至少一种操作模式，具有在以预定操作模式操作时由处理单元可编程的访问字段。 当访问字段被设置时，处理单元被选择性地拒绝对相关联的至少一个模式特定寄存器的访问，由此在切换操作期间避免在相关联的至少一个模式特定寄存器中更新数据值。 这显着提高了开关操作的速度。

公开(公告)号：US07325083B2

公开(公告)日：2008-01-29

申请号：US10714516

申请日：2003-11-17

申请人： Simon Charles Watt ,  Christopher Bentley Dornan ,  Luc Orion ,  Nicolas Chaussade ,  Lionel Belnet ,  Stephane Eric Brochier ,  David Hennah Mansell ,  Dominic Hugo Symes

发明人： Simon Charles Watt ,  Christopher Bentley Dornan ,  Luc Orion ,  Nicolas Chaussade ,  Lionel Belnet ,  Stephane Eric Brochier ,  David Hennah Mansell ,  Dominic Hugo Symes

IPC分类号： G06F13/24

CPC分类号： G06F9/4812 ,  G06F9/45558 ,  G06F2009/45575 ,  G06F2009/45587

摘要： In a system supporting more than one operating system, a data processing thread executing on a first operating system may be subject to an interrupt which triggers interrupt handling on a second operating system. When that interrupt handling is completed on the second operating system, the first operating system is resumed using a return interrupt. The return interrupt specifies the data processing thread which is active on the second operating system such that an appropriate task switch or resumption may be made on the first operating system. The technique is particularly well suited to systems utilising a secure operating system and a non-secure operating system executing on the same hardware.

摘要翻译： 在支持多个操作系统的系统中，在第一操作系统上执行的数据处理线程可能受到在第二操作系统上触发中断处理的中断。 当在第二操作系统上完成该中断处理时，使用返回中断恢复第一操作系统。 返回中断指定在第二操作系统上活动的数据处理线程，使得可以在第一操作系统上进行适当的任务切换或恢复。 该技术特别适用于利用在相同硬件上执行的安全操作系统和非安全操作系统的系统。