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公开(公告)号：US11811390B2
公开(公告)日：2023-11-07
申请号：US16403639
申请日：2019-05-06
Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.
Inventor： You Qian , Humberto Campanella Pineda , Rakesh Kumar
Abstract: According to various embodiments, there is provided a resonator device that includes a first interdigital transducer and a second interdigital transducer that is electrically connected to the first interdigital transducer. Both the first interdigital transducer and the second interdigital transducer are configured to resonate at a common frequency. At least one of an electrode width and an electrode pitch of the first interdigital transducer is different from the respective electrode width and/or electrode pitch of the second interdigital transducer such that spurious peaks of the resonator device are lower in amplitude as compared to spurious peaks of each of the first interdigital transducer and the second interdigital transducer.
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公开(公告)号：US20230335583A1
公开(公告)日：2023-10-19
申请号：US17723665
申请日：2022-04-19
Applicant: GlobalFoundries Singapore Pte. Ltd.
Inventor： Jianbo Zhou , Shiang Yang Ong , Namchil Mun , Hung Chang Liao , Zhongxiu Yang
IPC: H01L21/762 , H01L29/06
CPC classification number: H01L29/0649 , H01L21/762
Abstract: Semiconductor structures including a deep trench isolation structure and methods of forming a semiconductor structure including a deep trench isolation structure. The semiconductor structure includes a semiconductor substrate having a device region, and a deep trench isolation structure in the semiconductor substrate. The deep trench isolation structure further includes a first portion, a second portion adjacent to the first portion, and a conductor layer in the first portion and the second portion. The conductor layer in the first portion of the deep trench isolation structure surrounds the device region. The conductor layer in the second portion of the deep trench isolation structure defines an electrical connection to the semiconductor substrate.
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公开(公告)号：US20230335580A1
公开(公告)日：2023-10-19
申请号：US17659834
申请日：2022-04-19
Applicant: GlobalFoundries Singapore Pte. Ltd.
Inventor： BONG WOONG MUN , JUAN BOON TAN , SZU HUAT GOH , JEOUNG MO KOO
IPC: H01L25/065 , H01L21/48 , H01L23/538 , H01L23/522 , H01L23/64 , H01L23/31 , H01L21/56 , H01L49/02 , H01L23/498
CPC classification number: H01L28/91 , H01L21/4857 , H01L21/486 , H01L21/565 , H01L23/3128 , H01L23/49816 , H01L23/49822 , H01L23/49838 , H01L23/5223 , H01L23/5383 , H01L23/5386 , H01L23/642 , H01L25/0655
Abstract: An electronic device is provided, the device comprising an interposer including a dielectric material and an interconnect structure. An integrated circuit chip may be arranged over the interposer. A galvanic capacitor may be spaced from the integrated circuit chip. The galvanic capacitor having a first electrode and a second electrode. The first electrode of the galvanic capacitor may be coupled to the integrated circuit chip. A molding material may be arranged over the integrated circuit chip and the galvanic capacitor, whereby the integrated circuit chip may be spaced from the galvanic capacitor by at least a portion of the molding material.
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公开(公告)号：US11793004B2
公开(公告)日：2023-10-17
申请号：US16994647
申请日：2020-08-16
Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.
Inventor： Desmond Jia Jun Loy , Eng Huat Toh , Shyue Seng Tan
CPC classification number: H10B63/34 , G11C7/18 , H10N70/8265 , H10N70/841 , H10N70/8836
Abstract: The present disclosure generally relates to memory devices and methods of forming the same. More particularly, the present disclosure relates to resistive random-access (ReRAM) memory devices. The present disclosure provides a memory device including a first electrode, a dielectric cap above the first electrode, a second electrode laterally adjacent to the first electrode, in which an upper surface of the second electrode is substantially coplanar with an upper surface of the dielectric cap, and a resistive layer between the first electrode and the second electrode. An edge of the first electrode is electrically coupled to an edge of the second electrode by at least the resistive layer.
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35.发明授权公开(公告)号：US11791083B2
公开(公告)日：2023-10-17
申请号：US17330934
申请日：2021-05-26
Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.
Inventor： Eng-Huat Toh , Hemant M. Dixit , Vinayak Bharat Naik , Kazutaka Yamane
CPC classification number: H01F10/3272 , G01R33/098 , H01F10/3254 , H01F41/32
Abstract: The present disclosure relates to integrated circuits, and more particularly, a tunnel magneto-resistive (TMR) sensor with perpendicular magnetic tunneling junction (p-MTJ) structures and methods of manufacture and operation. The structure includes: a first magnetic tunneling junction (MTJ) structure on a first level; a second MTJ structure on a same wiring level as the first MTJ structure; and at least one metal line between the first MTJ structure and the second MTJ structure.
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Patent Agency Ranking
公开(公告)号：US20230320104A1
公开(公告)日：2023-10-05
申请号：US17657363
申请日：2022-03-31
Applicant: GlobalFoundries Singapore Pte. Ltd.
Inventor： JIA RUI THONG , JIANXUN SUN , ENG HUAT TOH , JUAN BOON TAN
CPC classification number: H01L27/2436 , H01L45/1253 , H01L45/1608
Abstract: The disclosed subject matter relates generally to memory devices and a method of forming the same. More particularly, the present disclosure relates to three terminal resistive random-access (ReRAM) memory structures having two bottom electrodes and one top electrode. The present disclosure provides a structure including a first bottom electrode having an upper surface, a second bottom electrode having an upper surface, a switching layer on the upper surface of the first electrode and the upper surface of the second electrode, an oxygen enhancement layer on the switching layer, and a top electrode on the oxygen enhancement layer, the top electrode is positioned above the first bottom electrode and the second bottom electrode.
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公开(公告)号：US20230301087A1
公开(公告)日：2023-09-21
申请号：US17694846
申请日：2022-03-15
Applicant: GlobalFoundries Singapore Pte. Ltd.
Inventor： Bong Woong Mun , Jeoung Mo Koo
IPC: H01L27/11558
CPC classification number: H01L27/11558
Abstract: Embodiments of the disclosure provide a circuit structure and related multi-time programmable (MTP) memory cell. The circuit structure may include a transistor having a floating gate over a semiconductor channel and a control gate on the dielectric layer. The control gate is electrically coupled to a word line. The control gate is capacitively coupled to the floating gate. A metal-insulator-metal (MIM) capacitor includes a first electrode coupled to the word line and a second electrode coupled to the floating gate of the transistor.
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公开(公告)号：US11762042B2
公开(公告)日：2023-09-19
申请号：US17105675
申请日：2020-11-27
Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.
Inventor： Ping Zheng , Eng Huat Toh , Yongshun Sun
CPC classification number: G01R33/077 , H10N50/85 , H10N52/01 , H10N52/101
Abstract: A magnetic field sensor may include a semiconductor structure having a planar surface, and first, second, and third sensing devices. The semiconductor structure may include a semiconductor member having a two-dimensional electron gas therein, and an insulator member disposed on the semiconductor member. The first sensing device may be configured to sense magnetic field along a first axis parallel to the planar surface. The second sensing device may be configured to sense magnetic field along a second axis parallel to the planar surface, and orthogonal to the first axis. The third sensing device may be configured to sense a magnetic field along a third axis normal to the planar surface. Each of the first, second, and third sensing devices may be formed in the semiconductor structure and may include electrodes that extend from the insulator member to the two-dimensional electron gas.
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公开(公告)号：US11749672B2
公开(公告)日：2023-09-05
申请号：US17471190
申请日：2021-09-10
Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.
Inventor： Prantik Mahajan , Aloysius Priartanto Herlambang , Kyong Jin Hwang , Robert John Gauthier, Jr.
IPC: H01L27/02 , H01L27/06 , H01L21/762 , H01L21/8224
CPC classification number: H01L27/0248 , H01L21/76202 , H01L21/76224 , H01L21/8224 , H01L27/067 , H01L27/0658 , H01L27/0664
Abstract: A device includes a first region, a second region disposed on the first region, a third region and a fourth region abutting the third region disposed in the second region, a fifth region disposed in the third region and coupled to a collector disposed above, and a sixth region disposed in the fourth region and coupled to an emitter disposed above. A first isolation is disposed between the collector and the emitter. A seventh region is disposed in the fifth region and coupled to the collector is spaced apart from the first isolation. The first region, the third region, the fifth region, the collector and the emitter have a first conductivity type different from a second conductivity type that the second region, the fourth region, the sixth region and the seventh region have.
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公开(公告)号：US11744166B2
公开(公告)日：2023-08-29
申请号：US17007759
申请日：2020-08-31
Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.
Inventor： Lanxiang Wang , Shyue Seng Tan , Eng Huat Toh
CPC classification number: H10N70/841 , H10B63/00 , H10N70/063 , H10N70/8833
Abstract: Structures for a resistive memory element and methods of forming a structure for a resistive memory element. The resistive memory element has a first electrode, a second electrode, a third electrode, and a switching layer. The first electrode is coupled to the switching layer, the second electrode is coupled to a side surface of the switching layer, and the third electrode is coupled to the switching layer.
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