公开(公告)号：US20120119287A1

公开(公告)日：2012-05-17

申请号：US13297493

申请日：2011-11-16

Applicant: Sang-Yong PARK ,  Jintaek PARK ,  Hansoo KIM ,  Juhyuck CHUNG ,  Wonseok CHO

Inventor： Sang-Yong PARK ,  Jintaek PARK ,  Hansoo KIM ,  Juhyuck CHUNG ,  Wonseok CHO

IPC: H01L29/78

CPC classification number: H01L21/823475 ,  H01L27/11519 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11575 ,  H01L27/11582 ,  H01L29/7926

Abstract: A three dimensional (3D) semiconductor device includes; a vertical channel extending from a lower end proximate a substrate to an upper end and connecting a plurality of memory cells, and a cell array comprising the plurality of cells, wherein the cell array is arranged in a gate stack of layers having a stair-stepped structure disposed on the substrate. The gate stack includes a lower layer including a lower select line coupled to a lower non-memory transistor proximate the lower end, upper layers including conductive lines respectively coupled to an upper non-memory transistor proximate the upper end and connected as a single conductive piece to form an upper select line, and intermediate layers respectively including a word line and coupled to a cell transistor, wherein the intermediate layers are disposed between the lower select line and the upper select line.

Abstract translation: 三维（3D）半导体器件包括： 垂直通道，其从靠近基板的下端延伸到上端并连接多个存储单元;以及包括所述多个单元的单元阵列，其中所述单元阵列布置在具有台阶的层的栅堆叠中 结构设置在基板上。 栅极堆叠包括下层，其包括耦合到靠近下端的下部非存储晶体管的下部选择线，上层包括分别耦合到靠近上端的上部非存储晶体管的导线，并且作为单个导电片连接 以形成上部选择线，以及分别包括字线并耦合到单元晶体管的中间层，其中中间层设置在下部选择线和上部选择线之间。

公开(公告)号：US20120061744A1

公开(公告)日：2012-03-15

申请号：US13229136

申请日：2011-09-09

Applicant: SUNG-MIN HWANG ,  Hansoo Kim ,  Changseok Kang ,  Wonseok Cho ,  Jae-Joo Shim

Inventor： SUNG-MIN HWANG ,  Hansoo Kim ,  Changseok Kang ,  Wonseok Cho ,  Jae-Joo Shim

IPC: H01L27/105

CPC classification number: H01L27/11578 ,  H01L27/11565 ,  H01L27/11568 ,  H01L27/11573 ,  H01L27/11582

Abstract: Three dimensional semiconductor memory devices are provided. The three dimensional semiconductor memory device includes a first stacked structure and a second stacked structure sequentially stacked on a substrate. The first stacked structure includes first insulating patterns and first gate patterns which are alternately and repeatedly stacked on a substrate, and the second stacked structure includes second insulating patterns and second gate patterns which are alternately and repeatedly stacked on the first stacked structure. A plurality of first vertical active patterns penetrate the first stacked structure, and a plurality of second vertical active patterns penetrate the second stacked structure. The number of the first vertical active patterns is greater than the number of the second vertical active patterns.

Abstract translation: 提供三维半导体存储器件。 三维半导体存储器件包括顺序层叠在基板上的第一堆叠结构和第二堆叠结构。 第一堆叠结构包括在衬底上交替重复堆叠的第一绝缘图案和第一栅极图案，并且第二堆叠结构包括在第一堆叠结构上交替重复堆叠的第二绝缘图案和第二栅极图案。 多个第一垂直有源图案穿透第一堆叠结构，并且多个第二垂直有源图案穿透第二堆叠结构。 第一垂直有源图案的数量大于第二垂直有效图案的数量。

公开(公告)号：US08115259B2

公开(公告)日：2012-02-14

申请号：US12694339

申请日：2010-01-27

Applicant: Sunil Shim ,  Hansoo Kim ,  Jaehoon Jang ,  Jaehun Jeong

Inventor： Sunil Shim ,  Hansoo Kim ,  Jaehoon Jang ,  Jaehun Jeong

IPC: H01L21/70

CPC classification number: H01L27/11551 ,  G11C16/0483 ,  H01L27/11556 ,  H01L29/66825 ,  H01L29/7881

Abstract: A three-dimensional semiconductor device includes a semiconductor substrate, vertical channel structures arranged on the semiconductor substrate in a matrix, a P-type semiconductor layer disposed at the semiconductor substrate to be in direct with the vertical channel structures, and a common source line disposed at the semiconductor substrate between the vertical channel structures. The common source line may be in contact with the P-type semiconductor layer.

Abstract translation: 三维半导体器件包括：半导体衬底，以矩阵形式布置在半导体衬底上的垂直沟道结构;设置在半导体衬底处以与垂直沟道结构直接相连的P型半导体层;以及布置的公共源极线 在垂直沟道结构之间的半导体衬底处。 公共源极线可以与P型半导体层接触。

公开(公告)号：US20120033503A1

公开(公告)日：2012-02-09

申请号：US13176950

申请日：2011-07-06

Applicant: JUHYUNG KIM ,  Changseok Kang ,  Hansoo Kim ,  Byeong-In Choe

Inventor： JUHYUNG KIM ,  Changseok Kang ,  Hansoo Kim ,  Byeong-In Choe

IPC: G11C16/16

CPC classification number: G11C16/16 ,  G11C16/32

Abstract: An erase method of a charge trap flash memory device, the method including receiving a temperature detection result, and performing an erase operation based on the temperature detection result, wherein the erase operation includes an erase execution interval, an erase verify interval and a delay time between the erase execution interval and the erase verify interval, wherein the erase operation changes a level of a word line voltage applied to word lines during the erase execution interval, a length of the delay time, or a level of the word line voltage applied to the word lines during the delay time.

Abstract translation: 一种电荷捕捉闪存器件的擦除方法，该方法包括接收温度检测结果，并且基于温度检测结果执行擦除操作，其中擦除操作包括擦除执行间隔，擦除验证间隔和延迟时间 在所述擦除执行间隔和所述擦除验证间隔之间，其中所述擦除操作改变在所述擦除执行间隔期间施加到字线的字线电压的电平，所述延迟时间的长度，或施加到所述擦除执行间隔的字线电压的电平 延迟时间内的字线。

公开(公告)号：US20110065270A1

公开(公告)日：2011-03-17

申请号：US12858057

申请日：2010-08-17

Applicant: Sunil Shim ,  Jaehoon Jang ,  Hansoo Kim ,  Sungmi Hwang ,  Wonseok Cho ,  Jinsoo Lim

Inventor： Sunil Shim ,  Jaehoon Jang ,  Hansoo Kim ,  Sungmi Hwang ,  Wonseok Cho ,  Jinsoo Lim

IPC: H01L21/8229

CPC classification number: H01L29/7926 ,  H01L27/11556 ,  H01L27/11582

Abstract: A method of forming a semiconductor memory device includes stacking a plurality of alternating first insulating layers and first sacrificial layers on a substrate to form a first multilayer structure, forming a first hole through the first multilayer structure, forming a first semiconductor pattern in the first hole, stacking a plurality of alternating second insulating layers and second sacrificial layers on the first multilayer structure to form a second multilayer structure, forming a second hole through the second multilayer structure to be aligned with the first hole, forming a second semiconductor pattern in the second hole, forming a trench to expose sidewalls of the first and second insulating layers at a side of the first and second semiconductor patterns, removing at least some portions of the first and second sacrificial layers to form a plurality of recess regions, forming an information storage layer along surfaces of the plurality of recess regions, and forming a conductive pattern within each recess region.

Abstract translation: 一种形成半导体存储器件的方法包括在衬底上堆叠多个交替的第一绝缘层和第一牺牲层以形成第一多层结构，通过所述第一多层结构形成第一孔，在所述第一孔中形成第一半导体图案 在所述第一多层结构上堆叠多个交替的第二绝缘层和第二牺牲层以形成第二多层结构，通过所述第二多层结构形成与所述第一孔对准的第二孔，在所述第二多层结构中形成第二半导体图案 形成沟槽，以在第一和第二半导体图案的一侧露出第一绝缘层和第二绝缘层的侧壁，去除第一和第二牺牲层的至少一部分以形成多个凹陷区域，形成信息存储器 层，并且形成导电体 每个凹陷区域内的图案。

公开(公告)号：US20100315875A1

公开(公告)日：2010-12-16

申请号：US12860049

申请日：2010-08-20

Applicant: Doogon Kim ,  Sunil Shim ,  Hansoo Kim ,  Wonseok Cho ,  Jaehoon Jang ,  Jaehun Jeong

Inventor： Doogon Kim ,  Sunil Shim ,  Hansoo Kim ,  Wonseok Cho ,  Jaehoon Jang ,  Jaehun Jeong

IPC: G11C16/04

CPC classification number: G11C16/10 ,  G11C16/0483 ,  H01L27/11524 ,  H01L27/11551 ,  H01L27/11556 ,  H01L29/66825 ,  H01L29/7881

Abstract: Provided is a method of operating a non-volatile memory device. The method includes applying a turn-on voltage to each of first and second string select transistors of a first NAND string, applying first and second voltages to third and fourth string select transistors of a second NAND string, respectively, and applying a high voltage to word lines connected with memory cells of the first and second NAND strings.

Abstract translation: 提供了一种操作非易失性存储器件的方法。 该方法包括对第一NAND串的第一和第二串选择晶体管中的每一个施加导通电压，将第一和第二电压分别施加到第二NAND串的第三和第四串选择晶体管，并将高电压施加到 与第一和第二NAND串的存储单元相连的字线。

公开(公告)号：US20100224929A1

公开(公告)日：2010-09-09

申请号：US12718108

申请日：2010-03-05

Applicant: Jaehun Jeong ,  Hansoo Kim ,  Jaehoon Jang ,  Sunil Shim ,  Suyoun Lee

Inventor： Jaehun Jeong ,  Hansoo Kim ,  Jaehoon Jang ,  Sunil Shim ,  Suyoun Lee

IPC: H01L29/792 ,  H01L29/788

CPC classification number: H01L27/11568 ,  H01L27/11578 ,  H01L27/11582

Abstract: A vertical NAND string nonvolatile memory device can include an upper dopant region disposed at an upper portion of an active pattern and can have a lower surface located a level higher than an upper surface of an upper selection gate pattern. A lower dopant region can be disposed at a lower portion of the active pattern and can have an upper surface located at a level lower than a lower surface of a lower selection gate pattern.

Abstract translation: 垂直NAND串非易失性存储器件可以包括设置在有源图案的上部的上部掺杂剂区域，并且可以具有位于比上部选择栅极图案的上表面高的电平的下表面。 下掺杂剂区域可以设置在有源图案的下部，并且可以具有位于比下选择栅图案的下表面低的水平的上表面。

公开(公告)号：US10199116B2

公开(公告)日：2019-02-05

申请号：US15664303

申请日：2017-07-31

Applicant: Sun-Il Shim ,  Jae-Hoon Jang ,  Donghyuk Chae ,  Youngho Lim ,  Hansoo Kim ,  Jaehun Jeong

Inventor： Sun-Il Shim ,  Jae-Hoon Jang ,  Donghyuk Chae ,  Youngho Lim ,  Hansoo Kim ,  Jaehun Jeong

IPC: G11C16/10 ,  G11C16/34 ,  G11C16/04 ,  H01L27/11582 ,  G11C16/08 ,  G11C16/12 ,  G11C16/14 ,  G11C16/26 ,  H01L27/1157

Abstract: Nonvolatile memory devices, operating methods thereof, and memory systems including the same. A nonvolatile memory device may include a memory cell array and a word line driver. The memory cell array may include a plurality of memory cells. The word line driver may be configured to apply word line voltages to a plurality of word lines connected to the plurality of memory cells, respectively. Magnitudes of the word line voltages may be determined according to locations of the plurality of word lines.

公开(公告)号：US20180196147A1

公开(公告)日：2018-07-12

申请号：US15739873

申请日：2016-03-02

Applicant: Changgoo KANG ,  Jangho HA ,  Joonho OH ,  Hansoo KIM ,  Youngsoo KIM ,  Manhee JEONG

Inventor： Changgoo KANG ,  Jangho HA ,  Joonho OH ,  Hansoo KIM ,  Youngsoo KIM ,  Manhee JEONG

IPC: G01T1/20 ,  G01T1/202

CPC classification number: G01T1/2006 ,  G01T1/20 ,  G01T1/2002 ,  G01T1/2023

Abstract: The present invention provides a radiation detector comprising: a scintillator for absorbing radiation to generate light; and a light detector formed in the scintillator, wherein the scintillator is composed of a two-dimensional nanomaterial for imparting ductility. The scintillator is formed by laminating the two-dimensional nanomaterial, the two-dimensional nanomaterial being at least one of graphene oxide, reduced graphene oxide, and graphene quantum dots.

公开(公告)号：US20160111440A1

公开(公告)日：2016-04-21

申请号：US14973182

申请日：2015-12-17

Applicant: Soodoo Chae ,  Myoungbum Lee ,  HuiChang Moon ,  Hansoo Kim ,  JinGyun Kim ,  Kihyun Kim ,  Siyoung Choi ,  Hoosung Cho

Inventor： Soodoo Chae ,  Myoungbum Lee ,  HuiChang Moon ,  Hansoo Kim ,  JinGyun Kim ,  Kihyun Kim ,  Siyoung Choi ,  Hoosung Cho

IPC: H01L27/115 ,  H01L29/40 ,  H01L23/535 ,  H01L29/423

CPC classification number: H01L27/11582 ,  H01L23/49844 ,  H01L23/5226 ,  H01L23/535 ,  H01L27/11565 ,  H01L27/11575 ,  H01L27/11578 ,  H01L29/408 ,  H01L29/4234 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A three-dimensional nonvolatile memory device and a method for fabricating the same include a semiconductor substrate, a plurality of active pillars, a plurality of gate electrodes, and a plurality of supporters. The semiconductor substrate includes a memory cell region and a contact region. The active pillars extend in the memory cell region perpendicularly to the semiconductor substrate. The gate electrodes intersect the active pillars, extend from the memory cell region to the contact region and are stacked on the semiconductor substrate. The supporters extend in the contact region perpendicularly to the semiconductor substrate to penetrate at least one or more of the gate electrodes.

Abstract translation: 三维非易失性存储器件及其制造方法包括半导体衬底，多个有源柱，多个栅电极和多个支撑体。 半导体衬底包括存储单元区域和接触区域。 活性柱在垂直于半导体衬底的存储单元区域中延伸。 栅电极与活性柱相交，从存储单元区延伸到接触区，并且堆叠在半导体衬底上。 支撑体在接触区域中垂直于半导体衬底延伸以穿透至少一个或多个栅电极。