公开(公告)号：US20050162898A1

公开(公告)日：2005-07-28

申请号：US11081652

申请日：2005-03-17

Applicant: Hasan Nejad ,  Mirmajid Seyyedy

Inventor： Hasan Nejad ,  Mirmajid Seyyedy

IPC: G11C11/15 ,  G11C11/16 ,  H01L21/8246 ,  H01L27/22 ,  G11C11/00

CPC classification number: G11C11/16 ,  B82Y10/00 ,  G11C11/15 ,  H01L27/228

Abstract: This invention relates to MRAM technology and new variations on MRAM array architecture to incorporate certain advantages from both cross-point and 1T-1MTJ architectures. The fast read-time and higher signal-to-noise ratio of the 1T-1MTJ architecture and the higher packing density of the cross-point architecture are both exploited by combining certain characteristics of these layouts. A single access transistor 16 is used to read multiple MRAM cells, which can be stacked vertically above one another in a plurality of MRAM array layers arranged in a “Z” axis direction.

Abstract translation: 本发明涉及MRAM技术和MRAM阵列体系结构的新变型，其中包含了来自交叉点和1T-1MTJ架构的某些优点。 通过组合这些布局的某些特性，可以利用1T-1MTJ架构的快速读取时间和更高的信噪比以及交叉点架构的更高的封装密度。 单个访问晶体管16用于读取多个MRAM单元，其可以在以“Z”轴方向布置的多个MRAM阵列层中彼此垂直堆叠堆叠。

公开(公告)号：US06882566B2

公开(公告)日：2005-04-19

申请号：US10895975

申请日：2004-07-22

Applicant: Hasan Nejad ,  Mirmajid Seyyedy

Inventor： Hasan Nejad ,  Mirmajid Seyyedy

IPC: G11C11/15 ,  G11C11/16 ,  H01L21/8246 ,  H01L27/22 ,  G11C11/14

CPC classification number: G11C11/16 ,  B82Y10/00 ,  G11C11/15 ,  H01L27/228

Abstract: This invention relates to MRAM technology and new variations on MRAM array architecture to incorporate certain advantages from both cross-point and 1T-1MTJ architectures. The fast read-time and higher signal-to-noise ratio of the 1T-1MTJ architecture and the higher packing density of the cross-point architecture are both exploited by combining certain characteristics of these layouts. A single access transistor 16 is used to read multiple MRAM cells, which can be stacked vertically above one another in a plurality of MRAM array layers arranged in a “Z” axis direction.

Abstract translation: 本发明涉及MRAM技术和MRAM阵列体系结构的新变型，其中包含了来自交叉点和1T-1MTJ架构的某些优点。 通过组合这些布局的某些特性，可以利用1T-1MTJ架构的快速读取时间和更高的信噪比以及交叉点架构的更高的封装密度。 单个访问晶体管16用于读取多个MRAM单元，其可以在以“Z”轴方向布置的多个MRAM阵列层中彼此垂直堆叠堆叠。

公开(公告)号：US20050040453A1

公开(公告)日：2005-02-24

申请号：US10920740

申请日：2004-08-17

Applicant: Hasan Nejad ,  James Deak

Inventor： Hasan Nejad ,  James Deak

IPC: H01L21/00 ,  H01L21/8238 ,  H01L27/108 ,  H01L27/22 ,  H01L29/76 ,  H01L43/12

CPC classification number: H01L27/222

Abstract: The invention includes a construction comprising an MRAM device between a pair of conductive lines. Each of the conductive lines can generate a magnetic field encompassing at least a portion of the MRAM device. Each of the conductive lines is surrounded on three sides by magnetic material to concentrate the magnetic fields generated by the conductive lines at the MRAM device. The invention also includes a method of forming an assembly containing MRAM devices. A plurality of MRAM devices are formed over a substrate. An electrically conductive material is formed over the MRAM devices, and patterned into a plurality of lines. The lines are in a one-to-one correspondence with the MRAM devices and are spaced from one another. After the conductive material is patterned into lines, a magnetic material is formed to extend over the lines and within spaces between the lines.

Abstract translation: 本发明包括在一对导线之间包括MRAM器件的结构。 每个导线可以产生包围MRAM装置的至少一部分的磁场。 每个导线在三面被磁性材料包围以将由导线产生的磁场集中在MRAM器件上。 本发明还包括形成包含MRAM器件的组件的方法。 在衬底上形成多个MRAM器件。 导电材料形成在MRAM器件上，并被图案化成多条线。 这些线与MRAM器件一一对应，并且彼此间隔开。 在将导电材料图案化成线之后，形成磁性材料以在线之间和线之间的空间内延伸。

公开(公告)号：US06828639B2

公开(公告)日：2004-12-07

申请号：US10198194

申请日：2002-07-17

Applicant: Hasan Nejad ,  James G. Deak

Inventor： Hasan Nejad ,  James G. Deak

IPC: H01L2714

CPC classification number: H01L27/222 ,  G11C11/15 ,  H01L43/08 ,  H01L43/12

Abstract: MRAM structures employ the magnetic properties of layered magnetic and non-magnetic materials to read memory storage logic states. Improvements in switching reliability may be achieved by altering the shape of the layered magnetic stack structure. Forming recessed regions with sloped interior walls in an ILD layer prior to depositing the layered magnetic stack structure produces a significant advantage over the prior art by allowing a CMP process to be used to define the magnetic bit shapes. The sloped interior walls of the recessed regions, which is singular to the present invention, provide a unique formation and shaping of the magnetic stack structure, which may reduce the magnetic coupling effect between magnetic layers of the magnetic stack structure.

Abstract translation: MRAM结构采用分层磁性和非磁性材料的磁性来读取存储器存储逻辑状态。 可以通过改变分层磁堆栈结构的形状来实现开关可靠性的改进。 在沉积分层磁堆栈结构之前，在ILD层中形成具有倾斜内壁的凹陷区域通过允许使用CMP工艺来定义磁头形状而产生比现有技术更大的优点。 凹陷区域的倾斜内壁，对于本发明而言是单一的，提供了磁性堆叠结构的独特的形成和成形，这可以减小磁性堆叠结构的磁性层之间的磁耦合效应。

公开(公告)号：US08592797B2

公开(公告)日：2013-11-26

申请号：US13591891

申请日：2012-08-22

Applicant: Hasan Nejad

Inventor： Hasan Nejad

IPC: H01L47/00

CPC classification number: H01L27/2436 ,  H01L27/2472 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1273 ,  H01L45/144 ,  H01L45/16

Abstract: A variable resistance memory element and method of forming the same. The memory element includes a substrate supporting a bottom electrode having a small bottom contact area. A variable resistance material is formed over the bottom electrodes such that the variable resistance material has a surface that is in electrical communication with the bottom electrode and a top electrode is formed over the variable resistance material. The small bottom electrode contact area reduces the reset current requirement which in turn reduces the write transistor size for each bit.

公开(公告)号：US08354661B2

公开(公告)日：2013-01-15

申请号：US13166362

申请日：2011-06-22

Applicant: Hasan Nejad

Inventor： Hasan Nejad

IPC: H01L47/00

CPC classification number: H01L27/2436 ,  H01L27/2472 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1273 ,  H01L45/144 ,  H01L45/16

Abstract: A variable resistance memory element and method of forming the same. The memory element includes a substrate supporting a bottom electrode having a small bottom contact area. A variable resistance material is formed over the bottom electrodes such that the variable resistance material has a surface that is in electrical communication with the bottom electrode and a top electrode is formed over the variable resistance material. The small bottom electrode contact area reduces the reset current requirement which in turn reduces the write transistor size for each bit.

Abstract translation: 一种可变电阻记忆元件及其形成方法。 存储元件包括支撑具有小的底部接触区域的底部电极的衬底。 在底部电极上形成可变电阻材料，使得可变电阻材料具有与底部电极电连通的表面，并且顶部电极形成在可变电阻材料上。 小的底部电极接触面积减小了复位电流要求，进而降低了每个位的写入晶体管尺寸。

公开(公告)号：US20110303889A1

公开(公告)日：2011-12-15

申请号：US13166362

申请日：2011-06-22

Applicant: Hasan Nejad

Inventor： Hasan Nejad

IPC: H01L27/26

CPC classification number: H01L27/2436 ,  H01L27/2472 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1273 ,  H01L45/144 ,  H01L45/16

Abstract: A variable resistance memory element and method of forming the same. The memory element includes a substrate supporting a bottom electrode having a small bottom contact area. A variable resistance material is formed over the bottom electrodes such that the variable resistance material has a surface that is in electrical communication with the bottom electrode and a top electrode is formed over the variable resistance material. The small bottom electrode contact area reduces the reset current requirement which in turn reduces the write transistor size for each bit.

Abstract translation: 一种可变电阻记忆元件及其形成方法。 存储元件包括支撑具有小的底部接触区域的底部电极的衬底。 在底部电极上形成可变电阻材料，使得可变电阻材料具有与底部电极电连通的表面，并且顶部电极形成在可变电阻材料上。 小的底部电极接触面积减小了复位电流要求，进而降低了每个位的写入晶体管尺寸。

公开(公告)号：US07978491B2

公开(公告)日：2011-07-12

申请号：US12010651

申请日：2008-01-28

Applicant: Hasan Nejad ,  Mirmajid Seyyedy

Inventor： Hasan Nejad ,  Mirmajid Seyyedy

IPC: G11C7/02

CPC classification number: H01L27/228 ,  B82Y10/00 ,  G11C11/15 ,  G11C11/16 ,  G11C13/004 ,  G11C2013/0054 ,  H01L27/2481

Abstract: This invention relates to memory technology and new variations on memory array architecture to incorporate certain advantages from both cross-point and 1T-1Cell architectures. The fast read-time and higher signal-to-noise ratio of the 1T-1Cell architecture and the higher packing density of the cross-point architecture are both exploited by combining certain characteristics of these layouts. A single access transistor 16 is used to read multiple memory cells, which can be stacked vertically above one another in a plurality of memory array layers arranged in a “Z” axis direction.

Abstract translation: 本发明涉及存储器技术以及存储器阵列结构的新变化，以便从交叉点和1T-1Cell架构中融入某些优点。 通过组合这些布局的某些特性，可以利用1T-1Cell架构的快速读取时间和更高的信噪比以及交叉点架构的更高的打包密度。 单个访问晶体管16用于读取可以以“Z”轴方向布置的多个存储器阵列层中的彼此垂直堆叠的多个存储单元。

公开(公告)号：US07932173B2

公开(公告)日：2011-04-26

申请号：US12121258

申请日：2008-05-15

Applicant: Hasan Nejad ,  James E. Green

Inventor： Hasan Nejad ,  James E. Green

IPC: H01L21/00

CPC classification number: H01L21/76838 ,  H01L21/76805 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The invention includes methods of fabricating integrated circuitry. In one implementation, at least two different elevation conductive metal lines are formed relative to a substrate. Then, interconnecting vias are formed in a common masking step between, a) respective of the at least two different elevation conductive metal lines, and b) respective conductive nodes. Interconnecting conductive metal is provided within the interconnecting vias. Other aspects and implementations are contemplated.

Abstract translation: 本发明包括制造集成电路的方法。 在一个实施方案中，相对于基底形成至少两个不同的高度导电金属线。 然后，互连通孔形成在a）相应的至少两个不同高度的导电金属线之间的公共掩模步骤中，以及b）相应的导电节点。 在互连通孔内提供互连导电金属。 考虑了其他方面和实现。

公开(公告)号：US07440339B2

公开(公告)日：2008-10-21

申请号：US11142448

申请日：2005-06-02

Applicant: Hasan Nejad ,  Mirmajid Seyyedy

Inventor： Hasan Nejad ,  Mirmajid Seyyedy

IPC: G11C7/10

CPC classification number: H01L27/228 ,  G11C5/02 ,  G11C11/16

Abstract: This invention relates to an MRAM array architecture which incorporates certain advantages from both cross-point and 1T-1MTJ architectures during reading operations. The fast read-time and higher signal to noise ratio of the 1T-1MTJ architecture and the higher packing density of the cross-point architecture are both exploited by using a single access transistor to control the reading of multiple stacked columns of MRAM cells each column being provided in a respective stacked memory layer.

Abstract translation: 本发明涉及一种在读取操作期间结合来自交叉点和1T-1MTJ架构的某些优点的MRAM阵列体系结构。 通过使用单个访问晶体管来控制1T-1MTJ架构的快速读取时间和更高的信噪比以及交叉点架构的更高的封装密度，以控制每个列的多个堆叠列的MRAM单元的读数 设置在相应的堆叠存储层中。