公开(公告)号：US20100164084A1

公开(公告)日：2010-07-01

申请号：US12347365

申请日：2008-12-31

Applicant: Jun-Ho LEE ,  Hyung-Dong Lee ,  Hyun-Seok Kim

Inventor： Jun-Ho LEE ,  Hyung-Dong Lee ,  Hyun-Seok Kim

IPC: H01L23/06 ,  H01L23/52 ,  H01G4/228 ,  H01L25/16

CPC classification number: H01L23/5223 ,  H01G4/232 ,  H01G4/30 ,  H01G4/33 ,  H01G4/40 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/642 ,  H01L25/0657 ,  H01L2224/05001 ,  H01L2224/05009 ,  H01L2224/05568 ,  H01L2224/0557 ,  H01L2224/056 ,  H01L2224/16146 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/19104 ,  H01L2224/05099

Abstract: Provided is a semiconductor device capable of removing a power ground grid noise using a small area. The semiconductor device includes a first chip including at least one decoupling capacitor; and a second semiconductor chip stacked over the first semiconductor chip, including internal circuits.

Abstract translation: 提供能够使用小面积去除电力接地电网噪声的半导体器件。 该半导体器件包括：包括至少一个去耦电容器的第一芯片; 以及堆叠在第一半导体芯片上的第二半导体芯片，包括内部电路。

公开(公告)号：US20070069784A1

公开(公告)日：2007-03-29

申请号：US11482684

申请日：2006-07-06

Applicant: Dong-Suk Shin ,  In-Hwa Jung ,  Jin-Han Kim ,  Chulwoo Kim ,  Hyung-Dong Lee

Inventor： Dong-Suk Shin ,  In-Hwa Jung ,  Jin-Han Kim ,  Chulwoo Kim ,  Hyung-Dong Lee

IPC: H03K5/12

CPC classification number: H03K19/00384 ,  H03K17/163 ,  H03K17/6872 ,  H03K2005/00123 ,  H03K2005/0013 ,  H03K2005/00143

Abstract: A slew-rate controlled output driver for use in a semiconductor device includes a PVT variation detection unit having a delay line for receiving a reference clock in order to detect a delay amount variation of the delay line determined according to process, voltage and temperature (PVT) variation; a selection signal generation unit for generating a driving selection signal which corresponds to a detection signal generated by the PVT variation detection unit; and an output driving unit having a plurality of driver units controlled by an output data and the driving selection signal for driving an output terminal with a driving strength which corresponds to the PVT variation.

Abstract translation: 用于半导体器件的转换速率控制输出驱动器包括具有用于接收参考时钟的延迟线的PVT变化检测单元，以便检测根据处理，电压和温度（PVT）确定的延迟线的延迟量变化 ）变异 选择信号生成单元，用于产生对应于由PVT变化检测单元生成的检测信号的驱动选择信号; 以及输出驱动单元，其具有由输出数据控制的多个驱动器单元和用于以对应于PVT变化的驱动强度来驱动输出端子的驱动选择信号。

公开(公告)号：US09465863B2

公开(公告)日：2016-10-11

申请号：US13304479

申请日：2011-11-25

Applicant: Hyung-dong Lee ,  Seung-taek Park ,  Hee-seon Park ,  Hae-dong Yeo

Inventor： Hyung-dong Lee ,  Seung-taek Park ,  Hee-seon Park ,  Hae-dong Yeo

IPC: G06F17/30

CPC classification number: G06F17/30702 ,  G06F17/30867

Abstract: A content-providing method and system, including identifying a representative type cluster by clustering content related to behavioral data which represents a use history of a user, according to type of the content, mapping the representative type cluster to a time interval, and storing the representative type cluster and the time interval.

Abstract translation: 一种内容提供方法和系统，包括：根据所述内容的类型，将所述代表类型集群映射到时间间隔，通过聚集与表示用户的使用历史的行为数据相关的内容来识别代表性类型集群;以及存储 代表型集群和时间间隔。

公开(公告)号：US09166162B2

公开(公告)日：2015-10-20

申请号：US13595324

申请日：2012-08-27

Applicant: Sung-Joon Yoon ,  Hyung-Dong Lee

Inventor： Sung-Joon Yoon ,  Hyung-Dong Lee

IPC: H01L29/02 ,  H01L45/00 ,  H01L27/24

CPC classification number: H01L45/146 ,  H01L27/2481 ,  H01L45/08 ,  H01L45/1233

Abstract: A resistive memory device includes: a memory cell comprising first and second electrodes and a resistive layer formed therebetween, wherein the resistive layer is formed of a resistance change material; and a strained film formed adjacent to the resistive layer and configured to apply a strain to the resistive layer.

Abstract translation: 电阻式存储器件包括：存储单元，包括第一和第二电极以及在其间形成的电阻层，其中所述电阻层由电阻变化材料形成; 以及形成在所述电阻层附近并被配置为向所述电阻层施加应变的应变膜。

公开(公告)号：US08811101B2

公开(公告)日：2014-08-19

申请号：US13399643

申请日：2012-02-17

Applicant: Hyung Gyun Yang ,  Hyung Dong Lee ,  Yong Kee Kwon ,  Young Suk Moon ,  Sung Wook Kim ,  Keun Hyung Kim

Inventor： Hyung Gyun Yang ,  Hyung Dong Lee ,  Yong Kee Kwon ,  Young Suk Moon ,  Sung Wook Kim ,  Keun Hyung Kim

IPC: G11C7/00 ,  G11C29/00

CPC classification number: G11C29/48 ,  G11C2029/0401

Abstract: A system in package (SIP) semiconductor system includes a memory device, a controller, a first input/output terminal, a test control unit, and a second input/output terminal. The controller communicates with the memory device. The first input/output terminal performs communication between the controller and a device external to the SIP semiconductor system. The test control unit controls a predetermined test mode of the memory device. The second input/output terminal performs communication between the test control unit and at least the device external to the SIP semiconductor system.

Abstract translation: 封装（SIP）半导体系统包括存储器件，控制器，第一输入/输出端子，测试控制单元和第二输入/输出端子。 控制器与存储器件通信。 第一输入/输出端子执行控制器与SIP半导体系统外部的设备之间的通信。 测试控制单元控制存储器件的预定测试模式。 第二输入/输出端子执行测试控制单元与至少在SIP半导体系统外部的设备之间的通信。

公开(公告)号：US20130299770A1

公开(公告)日：2013-11-14

申请号：US13595324

申请日：2012-08-27

Applicant: Sung-Joon YOON ,  Hyung-Dong LEE

Inventor： Sung-Joon YOON ,  Hyung-Dong LEE

IPC: H01L45/00

CPC classification number: H01L45/146 ,  H01L27/2481 ,  H01L45/08 ,  H01L45/1233

Abstract: A resistive memory device includes: a memory cell comprising first and second electrodes and a resistive layer formed therebetween, wherein the resistive layer is formed of a resistance change material; and a strained film formed adjacent to the resistive layer and configured to apply a strain to the resistive layer.

Abstract translation: 电阻式存储器件包括：存储单元，包括第一和第二电极以及在其间形成的电阻层，其中所述电阻层由电阻变化材料形成; 以及形成在所述电阻层附近并被配置为向所述电阻层施加应变的应变膜。

公开(公告)号：US20130246867A1

公开(公告)日：2013-09-19

申请号：US13603597

申请日：2012-09-05

Applicant: Hyung-Gyun YANG ,  Hyung-Dong LEE ,  Yong-Kee KWON ,  Young-Suk MOON ,  Hong-Sik KIM

Inventor： Hyung-Gyun YANG ,  Hyung-Dong LEE ,  Yong-Kee KWON ,  Young-Suk MOON ,  Hong-Sik KIM

IPC: G11C29/10 ,  G06F11/263

CPC classification number: G11C29/56 ,  G11C2029/5606

Abstract: This technology relates to smoothly performing a test on a memory circuit having a high memory capacity while reducing the size of a test circuit. A test circuit according to the present invention includes a test execution unit configured to perform a test on a target test memory circuit, an internal storage unit configured to store data for the test execution unit, and a conversion setting unit configured to set a part of or the entire storage space of the target test memory circuit as an external storage unit for storing the data for the test execution unit.

Abstract translation: 该技术涉及在减小测试电路的尺寸的同时平滑地对具有高存储容量的存储器电路进行测试。 根据本发明的测试电路包括被配置为对目标测试存储器电路进行测试的测试执行单元，被配置为存储用于测试执行单元的数据的内部存储单元，以及转换设置单元， 或作为用于存储测试执行单元的数据的外部存储单元的目标测试存储器电路的整个存储空间。

公开(公告)号：US20130092936A1

公开(公告)日：2013-04-18

申请号：US13341299

申请日：2011-12-30

Applicant: Hyung Gyun YANG ,  Hyung Dong LEE ,  Yong Kee KWON ,  Young Suk MOON ,  Sung Wook KIM

Inventor： Hyung Gyun YANG ,  Hyung Dong LEE ,  Yong Kee KWON ,  Young Suk MOON ,  Sung Wook KIM

IPC: H01L23/522

CPC classification number: H01L25/065 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor apparatus includes first and second vias, a first circuit unit, a second circuit unit and a third circuit unit. The first and second vias electrically connect a first chip and a second chip with each other. The first circuit unit is disposed in the first chip, receives test data, and is connected with the first via. The second circuit unit is disposed in the first chip, and is connected with the second via and the first circuit unit. The third circuit unit is disposed in the second chip, and is connected with the first via. The first circuit unit outputs an output signal thereof to one of the first via and the second circuit unit in response to a first control signal.

Abstract translation: 半导体装置包括第一和第二通孔，第一电路单元，第二电路单元和第三电路单元。 第一和第二通孔将第一芯片和第二芯片彼此电连接。 第一电路单元设置在第一芯片中，接收测试数据，并与第一通孔连接。 第二电路单元设置在第一芯片中，并与第二通孔和第一电路单元连接。 第三电路单元设置在第二芯片中，并与第一通孔连接。 第一电路单元响应于第一控制信号将其输出信号输出到第一通孔和第二电路单元之一。

公开(公告)号：US20130031439A1

公开(公告)日：2013-01-31

申请号：US13532299

申请日：2012-06-25

Applicant: Young Suk MOON ,  Hyung Dong LEE ,  Yong Kee KWON ,  Hyung Gyun YANG ,  Sung Wook KIM

Inventor： Young Suk MOON ,  Hyung Dong LEE ,  Yong Kee KWON ,  Hyung Gyun YANG ,  Sung Wook KIM

IPC: H03M13/29 ,  G06F11/10 ,  H03M13/09

CPC classification number: G06F11/1048 ,  G11C5/04 ,  G11C2029/0411

Abstract: A semiconductor memory apparatus includes: a memory cell area including a plurality of memory cell arrays stacked therein, each memory cell array having a plurality of memory cells integrated and formed therein to store data and a plurality of through-lines formed therein to transmit signals; and a control logic area configured to generate parity bits using a data signal inputted to the memory cell area and transmit the generated parity bits and the data signal to different through-lines.

Abstract translation: 半导体存储装置包括：存储单元区域，包括堆叠在其中的多个存储单元阵列，每个存储单元阵列具有集成并形成在其中的多个存储单元，用于存储数据和形成在其中的多条通线以传输信号; 以及控制逻辑区域，被配置为使用输入到存储单元区域的数据信号来生成奇偶校验位，并将生成的奇偶校验位和数据信号发送到不同的通过线。

公开(公告)号：US08110892B2

公开(公告)日：2012-02-07

申请号：US12649452

申请日：2009-12-30

Applicant: Jeong-Woo Lee ,  Hyung-Dong Lee ,  Sang-Hoon Shin ,  Hyang-Hwa Choi

Inventor： Jeong-Woo Lee ,  Hyung-Dong Lee ,  Sang-Hoon Shin ,  Hyang-Hwa Choi

IPC: H01L23/52

CPC classification number: H01L25/0657 ,  H01L22/22 ,  H01L23/481 ,  H01L23/5258 ,  H01L2224/16 ,  H01L2225/06517 ,  H01L2225/06544 ,  H01L2924/3011

Abstract: A semiconductor device includes a plurality of stacked semiconductor chips; and a plurality of through-silicon vias (TSVs) including first TSVs and redundant TSVs and configured to commonly transfer a signal to the plurality of stacked semiconductor chips. At least one of the semiconductor chips includes a plurality of repair fuse units configured to store defect information as to at least one defect of the TSVs; and a plurality of latch units allocated to the respective TSVs and configured to store a plurality of signals indicating at least one TSV defect and outputted from the plurality of repair fuse units.

Abstract translation: 半导体器件包括多个堆叠的半导体芯片; 以及包括第一TSV和冗余TSV的多个穿硅通孔（TSV），并且被配置为共同地将信号传送到多个堆叠的半导体芯片。 半导体芯片中的至少一个包括多个修复熔丝单元，其被配置为存储关于TSV的至少一个缺陷的缺陷信息; 以及分配给各个TSV的多个锁存单元，并被配置为存储指示至少一个TSV缺陷并从多个修复熔丝单元输出的多个信号。