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公开(公告)号：US20120213022A1
公开(公告)日：2012-08-23
申请号：US13399643
申请日：2012-02-17
申请人： Hyung Gyun YANG , Hyung Dong LEE , Yong Kee KWON , Young Suk MOON , Sung Wook KIM , Keun Hyung KIM
发明人： Hyung Gyun YANG , Hyung Dong LEE , Yong Kee KWON , Young Suk MOON , Sung Wook KIM , Keun Hyung KIM
IPC分类号： G11C29/00
CPC分类号： G11C29/48 , G11C2029/0401
摘要： A system in package (SIP) semiconductor system includes a memory device, a controller, a first input/output terminal, a test control unit, and a second input/output terminal. The controller communicates with the memory device. The first input/output terminal performs communication between the controller and a device external to the SIP semiconductor system. The test control unit controls a predetermined test mode of the memory device. The second input/output terminal performs communication between the test control unit and at least the device external to the SIP semiconductor system.
摘要翻译： 封装（SIP）半导体系统包括存储器件，控制器，第一输入/输出端子，测试控制单元和第二输入/输出端子。 控制器与存储器件通信。 第一输入/输出端子执行控制器与SIP半导体系统外部的设备之间的通信。 测试控制单元控制存储器件的预定测试模式。 第二输入/输出端子执行测试控制单元与至少在SIP半导体系统外部的设备之间的通信。
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2.发明申请SEMICONDUCTOR SYSTEM, SEMICONDUCTOR MEMORY APPARATUS, AND METHOD FOR INPUT/OUTPUT OF DATA USING THE SAME 有权半导体系统，半导体存储装置和使用该数据的数据的输入/输出的方法公开(公告)号：US20120140584A1
公开(公告)日：2012-06-07
申请号：US13219656
申请日：2011-08-27
IPC分类号： G11C8/18
CPC分类号： G11C7/22 , G06F2213/0038 , G11C7/1063 , G11C7/1066 , G11C7/222 , G11C11/22
摘要： A semiconductor system, a semiconductor memory apparatus, and a method for input/output of data using the same are disclosed. The semiconductor system includes a controller and a memory apparatus where the controller is configured to transmit a clock signal, a data output command, an address signal, and a second strobe signal to a memory apparatus. The memory apparatus is configured to provide data to the controller in synchronization with the second strobe signal, and in response to the clock signal, the data output command, the address signal, and the second strobe signal received from the controller.
摘要翻译： 公开了一种半导体系统，半导体存储装置和使用其的数据的输入/输出方法。 半导体系统包括控制器和存储装置，其中控制器被配置为向存储装置发送时钟信号，数据输出命令，地址信号和第二选通信号。 存储装置被配置为与第二选通信号同步地向控制器提供数据，并且响应于从控制器接收到的时钟信号，数据输出命令，地址信号和第二选通信号。
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公开(公告)号：US20120273961A1
公开(公告)日：2012-11-01
申请号：US13219645
申请日：2011-08-27
IPC分类号： H01L23/48
CPC分类号： G11C5/025 , G11C5/063 , H01L23/642 , H01L25/0657 , H01L25/18 , H01L2224/16 , H01L2224/16145 , H01L2225/06541 , H01L2225/06565 , H01L2924/15311
摘要： A semiconductor apparatus includes a plurality of semiconductor chips which are stacked; and an auxiliary semiconductor chip configured to recover and transmit signals of the plurality of semiconductor chips through a plurality of through vias which extend vertically, at a predetermined time interval.
摘要翻译： 半导体装置包括堆叠的多个半导体芯片; 以及辅助半导体芯片，被配置为通过以预定时间间隔垂直延伸的多个通孔来恢复和发送多个半导体芯片的信号。
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公开(公告)号：US20130092936A1
公开(公告)日：2013-04-18
申请号：US13341299
申请日：2011-12-30
IPC分类号： H01L23/522
CPC分类号： H01L25/065 , H01L23/481 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor apparatus includes first and second vias, a first circuit unit, a second circuit unit and a third circuit unit. The first and second vias electrically connect a first chip and a second chip with each other. The first circuit unit is disposed in the first chip, receives test data, and is connected with the first via. The second circuit unit is disposed in the first chip, and is connected with the second via and the first circuit unit. The third circuit unit is disposed in the second chip, and is connected with the first via. The first circuit unit outputs an output signal thereof to one of the first via and the second circuit unit in response to a first control signal.
摘要翻译： 半导体装置包括第一和第二通孔，第一电路单元，第二电路单元和第三电路单元。 第一和第二通孔将第一芯片和第二芯片彼此电连接。 第一电路单元设置在第一芯片中，接收测试数据，并与第一通孔连接。 第二电路单元设置在第一芯片中，并与第二通孔和第一电路单元连接。 第三电路单元设置在第二芯片中，并与第一通孔连接。 第一电路单元响应于第一控制信号将其输出信号输出到第一通孔和第二电路单元之一。
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5.发明申请公开(公告)号：US20130031439A1
公开(公告)日：2013-01-31
申请号：US13532299
申请日：2012-06-25
CPC分类号： G06F11/1048 , G11C5/04 , G11C2029/0411
摘要： A semiconductor memory apparatus includes: a memory cell area including a plurality of memory cell arrays stacked therein, each memory cell array having a plurality of memory cells integrated and formed therein to store data and a plurality of through-lines formed therein to transmit signals; and a control logic area configured to generate parity bits using a data signal inputted to the memory cell area and transmit the generated parity bits and the data signal to different through-lines.
摘要翻译： 半导体存储装置包括：存储单元区域，包括堆叠在其中的多个存储单元阵列，每个存储单元阵列具有集成并形成在其中的多个存储单元，用于存储数据和形成在其中的多条通线以传输信号; 以及控制逻辑区域，被配置为使用输入到存储单元区域的数据信号来生成奇偶校验位，并将生成的奇偶校验位和数据信号发送到不同的通过线。
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6.发明申请METHOD FOR IMPLEMENTING SPARE LOGIC OF SEMICONDUCTOR MEMORY APPARATUS AND STRUCTURE THEREOF 审中-公开实现半导体存储器件及其结构的备用逻辑的方法公开(公告)号：US20130155753A1
公开(公告)日：2013-06-20
申请号：US13585455
申请日：2012-08-14
申请人： Young Suk MOON , Yong Kee KWON
发明人： Young Suk MOON , Yong Kee KWON
IPC分类号： G11C5/06
CPC分类号： G11C5/063 , G06F2217/72 , H01L23/5286 , H01L27/0207 , H01L27/11807 , H01L2027/11881 , H01L2924/0002 , H01L2924/00
摘要： A method for implementing a spare logic of a semiconductor memory apparatus includes the steps of: forming one or more contact conductive layers, which are independent, in a power line and an active area, respectively; and performing metal programming on the contact conductive layers formed in the power line and the active area to electrically couple the independent contact conductive layers formed in the power line and the active area.
摘要翻译： 一种用于实现半导体存储装置的备用逻辑的方法包括以下步骤：分别在电力线和有源区中形成独立的一个或多个接触导电层; 以及对形成在电力线和有源区域中的接触导电层执行金属编程，以电耦合形成在电力线和有源区域中的独立接触导电层。
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公开(公告)号：US20110074369A1
公开(公告)日：2011-03-31
申请号：US12649193
申请日：2009-12-29
申请人： Yong Kee KWON , Hyung Dong Lee , Young Park Kim
发明人： Yong Kee KWON , Hyung Dong Lee , Young Park Kim
CPC分类号： G11C11/4074 , G11C5/147 , G11C29/02 , G11C29/021 , G11C29/028
摘要： A semiconductor apparatus includes a reference voltage generation unit, a comparison voltage generation unit, and a calibration unit. The reference voltage generation unit is disposed in a reference die and configured to generate a reference voltage. The comparison voltage generation unit is disposed in a die stacked on the reference die and configured to generate a comparison voltage in response to a calibration control signal. The calibration unit is configured to compare a level of the reference voltage with a level of the comparison voltage and generate the calibration control signal.
摘要翻译： 半导体装置包括参考电压产生单元，比较电压产生单元和校准单元。 参考电压产生单元设置在参考管芯中，并被配置为产生参考电压。 比较电压产生单元设置在堆叠在参考管芯上的管芯中，并被配置为响应校准控制信号产生比较电压。 校准单元被配置为将参考电压的电平与比较电压的电平进行比较并产生校准控制信号。
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公开(公告)号：US20110068822A1
公开(公告)日：2011-03-24
申请号：US12956416
申请日：2010-11-30
申请人： Yong Kee KWON , Hyung Dong LEE
发明人： Yong Kee KWON , Hyung Dong LEE
IPC分类号： H03K17/16
CPC分类号： G11C7/1048 , G11C11/4096 , G11C11/4097
摘要： A data line termination circuit includes a swing-width sensing unit configured to sense a swing width of a voltage of a data line and output a sensed signal, and a variable termination unit configured to adjust a termination resistance value of the data line in response to the sensed signal. The swing-width sensing unit can sense if the swing width is less than or greater than a predetermined swing width, and the swing width of the voltage of the data line can be reduced or increased to maintain the voltage of the data line within a predetermined range.
摘要翻译： 数据线终端电路包括：摆动宽度检测单元，被配置为感测数据线的电压的摆幅并输出感测信号;以及可变终端单元，被配置为响应于所述数据线的终端电阻值 感测信号。 摆幅感测单元可以感测摆动宽度是否小于或大于预定的摆动宽度，并且可以减小或增加数据线的电压的摆动宽度，以将数据线的电压保持在预定的 范围。
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公开(公告)号：US20090256585A1
公开(公告)日：2009-10-15
申请号：US12403549
申请日：2009-03-13
申请人： Yong Kee KWON , Hyung Dong LEE
发明人： Yong Kee KWON , Hyung Dong LEE
IPC分类号： H03K17/16
CPC分类号： G11C7/1048 , G11C11/4096 , G11C11/4097
摘要： A data line termination circuit includes a swing-width sensing unit configured to sense a swing width of a voltage of a data line and output a sensed signal, and a variable termination unit configured to adjust a termination resistance value of the data line in response to the sensed signal. The swing-width sensing unit can sense if the swing width is less than or greater than a predetermined swing width, and the swing width of the voltage of the data line can be reduced or increased to maintain the voltage of the data line within a predetermined range.
摘要翻译： 数据线终端电路包括：摆动宽度检测单元，被配置为感测数据线的电压的摆幅并输出感测信号;以及可变终端单元，被配置为响应于所述数据线的终端电阻值 感测信号。 摆幅感测单元可以感测摆动宽度是否小于或大于预定的摆动宽度，并且可以减小或增加数据线的电压的摆动宽度，以将数据线的电压保持在预定的 范围。
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