公开(公告)号：US20040184587A1

公开(公告)日：2004-09-23

申请号：US10390229

申请日：2003-03-17

Applicant: Intersil Americas Inc.

Inventor： Christopher Ludeman

IPC: H04M011/00

CPC classification number: H04L12/40006

Abstract: A telecommunication interface integrates DSL and POTS components in a manner which effectively separates their bandwidth requirements from their power requirements. This is accomplished by powering the tip path and ring path amplifiers with a pair of transformer-coupled floating power supply-sourced voltages, and referencing respective like polarity inputs of the amplifiers to a differential voltage pair that is used to operate the subscriber loop, including providing loop current and controllably applying a ringing voltage to the POTS line.

Abstract translation: 电信接口以有效地将其带宽要求与其功率需求分开的方式集成DSL和POTS组件。 这是通过用一对变压器耦合的浮动电源源电压为尖端路径和环路放大器供电，并将放大器的相应相似的极性输入参考用于操作用户环路的差分电压对来实现的，包括 提供回路电流并可控制地向POTS线施加振铃电压。

公开(公告)号：US20040180485A1

公开(公告)日：2004-09-16

申请号：US10811360

申请日：2004-03-26

Applicant: Intersil Americas Inc.

Inventor： James D. Beasom

IPC: H01L021/336 ,  H01L021/8234

CPC classification number: H01L29/7813 ,  H01L27/0921 ,  H01L29/1095 ,  H01L29/165 ,  H01L29/7801 ,  H01L29/7809 ,  H01L29/7835

Abstract: An integrated circuit having a MOS structure with reduced parasitic bipolar transistor action. In one embodiment, a MOS integrated circuit device comprises a substrate having a working surface, at least one body region and for each body region a source and a layer of narrow band gap material. Each body region is formed in the substrate proximate the working surface of the substrate. Each layer of narrow band gap material is positioned in a portion of its associated body region and proximate the working surface of the substrate. Each layer of narrow band gap material has a band gap that is narrower than the band gap of the substrate in which each of the body regions are formed. Each source region is formed in an associated body region. At least a portion of each source region is also formed in an associated layer of narrow band gap material.

公开(公告)号：US20040130307A1

公开(公告)日：2004-07-08

申请号：US10725764

申请日：2003-12-02

Applicant: Intersil Americas Inc. State of Incorporation: Delaware

Inventor： Noel Dequina ,  Donald R. Preslar ,  Paul K. Sferrazza

IPC: G05F001/40

CPC classification number: H02M1/38 ,  H02M3/1588 ,  Y02B70/1466

Abstract: A control circuit for a switch mode DC-DC converter contains an arrangement of monitored LGATE, UGATE and PHASE node condition threshold detectors, outputs of which are processed in accordance with a switching control operator to ensure that each of an upper FET (UFET) and a lower FET (LFET) is completely turned off before the other FET begins conduction, thereby maintaining a dead time that exhibits no shoot-through current and is independent of the type of switching FET.

Abstract translation: 用于开关模式DC-DC转换器的控制电路包含监视的LGATE，UGATE和PHASE节点状态阈值检测器的布置，其输出根据切换控制算子进行处理，以确保上FET（UFET）和 在另一个FET开始导通之前，下部FET（LFET）完全关闭，从而保持不存在直通电流的死区时间，并且不依赖于开关FET的类型。

公开(公告)号：US20040124818A1

公开(公告)日：2004-07-01

申请号：US10685314

申请日：2003-10-14

Applicant: Intersil Americas Inc., ,  State of Corporation : Delaware

Inventor： Noel B. Dequina ,  Donald R. Preslar ,  Paul K. Sferrazza

IPC: G05F001/40

CPC classification number: H02M1/36 ,  H02M1/32 ,  H02M3/156 ,  H02M3/1588 ,  Y02B70/1466

Abstract: An over-voltage protection circuit prevents an anomaly, such as a short circuit in the upper-switched electronic device of a DC-DC power supply, from propagating to downstream circuitry. The over-voltage protection circuit, which includes an overvoltage sense resistor coupled between an output of the upper or high side FET and the gate of the lower FET, is operative to sense a short circuit fault condition in the circuit path through the upper FET during initial power up of the system. In response to this condition, the lower NFET device is turned on so as to provide an immediate by-pass of the overvoltage condition to ground, and thereby prevent excessive voltage from being applied by the output terminal to downstream powered circuitry.

Abstract translation: 过电压保护电路防止DC-DC电源的上部开关电子装置中的短路等异常传播到下游电路。 包括耦合在上侧FET或高侧FET的输出端与下部FET的栅极之间的过电压检测电阻器的过电压保护电路可操作以感测通过上部FET的电路中的短路故障状况 初始启动系统。 响应于这种情况，下部NFET器件导通，以便将过电压状态的瞬时旁路提供给地，从而防止输出端子向下游供电电路施加过大的电压。

公开(公告)号：US20040108913A1

公开(公告)日：2004-06-10

申请号：US10315836

申请日：2002-12-10

Applicant: Intersil Americas Inc.

Inventor： Lawrence G. Pearce ,  William David Bartlett

IPC: H03K007/08

CPC classification number: H03L7/0805 ,  H03K5/06 ,  H03K7/08 ,  H03L7/0812

Abstract: A tapped delay line generates a fractional clock pulse signal for controlling a PWM pulse generator, such as used in a DC-DC converter. Operational parameters of the tapped delay are adjusted to maintain a desired fractional precision of the duty-cycle of the PWM clock pulse signal. In a first, phase locked loop (PLL) based embodiment, the tapped delay line-based digital PWM pulse generator includes a compensating phase locked-loop formed around an auxiliary tapped delay line that implements the voltage controlled oscillator of the PLL. In a second embodiment, the PWM pulse generator is configured as an nullopen-loopnull tapped delay line phase detector architecture, which avoids having to correlate parameters of the PLL delay line with those of the PWM delay line.

Abstract translation: 抽头延迟线产生用于控制PWM脉冲发生器的分数时钟脉冲信号，例如在DC-DC转换器中使用的。 调整抽头延迟的操作参数以保持PWM时钟脉冲信号占空比的期望分数精度。 在基于锁相环（PLL）的第一实施例中，基于抽头的延迟线数字PWM脉冲发生器包括一个形成在辅助抽头延迟线周围的补偿锁相环，该延迟线实现PLL的压控振荡器。 在第二实施例中，PWM脉冲发生器被配置为“开环”抽头延迟线相位检测器架构，避免了将PLL延迟线的参数与PWM延迟线的参数相关联。

公开(公告)号：US20040090218A1

公开(公告)日：2004-05-13

申请号：US10691251

申请日：2003-10-22

Applicant: Intersil Americas Inc.

Inventor： Robert Haynes Isham

IPC: G05F001/40

CPC classification number: H02M3/1588 ,  H02M1/32 ,  Y02B70/1466

Abstract: A self-powered overvoltage protection circuit for a regulated DC-DC converter looks for the onset of a very large input voltage prior to regulation. In response to such a voltage during this interval, it turns on a low side electronic power switching device, in accordance with the voltage at one of the phase node and the regulated voltage output terminal from which the protection circuit derives its power. This provides a bypass path for an overvoltage that would otherwise be coupled from the regulated voltage output terminal to one or more load devices.

Abstract translation: 用于稳压DC-DC转换器的自供电过电压保护电路在调节之前寻找非常大的输入电压的开始。 响应于该间隔期间的这种电压，它根据保护电路从其产生功率的相位节点和调节电压输出端之一处的电压来接通低边电子功率开关装置。 这提供了用于过电压的旁路路径，否则过电压将从调节电压输出端子耦合到一个或多个负载装置。

公开(公告)号：US20040038473A1

公开(公告)日：2004-02-26

申请号：US10645709

申请日：2003-08-21

Applicant: Intersil Americas Inc.

Inventor： Rex Everett Lowther ,  William R. Young

IPC: H01L021/8238

CPC classification number: H01L28/10 ,  H01F17/0013 ,  H01F27/367 ,  H01L23/5223 ,  H01L23/5225 ,  H01L23/5227 ,  H01L27/08 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present invention relates to integrated circuits having symmetric inducting devices with a ground shield. In one embodiment, a symmetric inducting device for an integrated circuit comprises a substrate, a main metal layer and a shield. The substrate has a working surface. The main metal layer has at least one pair of current path regions. Each of the current path region pairs is formed in generally a regular polygonal shape that is generally symmetric about a plane of symmetry that is perpendicular to the working surface of the substrate. The shield is patterned into segments that are generally symmetric about the plane of symmetry. Medial portions of at least some segments of the shield are formed generally perpendicular to the plane of symmetry as the medial portions cross the plane of symmetry.

Abstract translation: 本发明涉及具有接地屏蔽的对称感应装置的集成电路。 在一个实施例中，用于集成电路的对称感应装置包括基板，主金属层和屏蔽。 基板具有工作表面。 主金属层具有至少一对电流通路区域。 每个电流通路区域对形成为大致对称的大致对称的正交多边形形状，该对称平面垂直于衬底的工作表面。 屏蔽被图案化成通常对称平面对称的段。 当中间部分穿过对称平面时，屏蔽件的至少一些部分的中间部分大致垂直于对称平面形成。

公开(公告)号：US20040007760A1

公开(公告)日：2004-01-15

申请号：US10194496

申请日：2002-07-11

Applicant: INTERSIL AMERICAS INC.

Inventor： Rex Everett Lowther

IPC: H01L029/00

CPC classification number: H01L28/10 ,  H01L27/08

Abstract: Inducting devices having a patterned ground shield with ribbing in an integrated circuit. In one embodiment, an inducting device comprises conductive turns to conduct current, a shield layer and a plurality of ribs. The shield layer is formed a select distance from the conductive turns. The shield layer is patterned into sections of shield to prevent eddy currents. The plurality of ribs are formed from a conductive layer that is positioned between the conductive turns and shield layer. Each rib is electrically coupled to a single associated section of shield. Moreover, each rib is more conductive than its associated section of shield to provide a less resistive current path than its associated section of shield.

Abstract translation: 在集成电路中具有带肋的图案化接地屏蔽的感应装置。 在一个实施例中，感应装置包括导电匝以传导电流，屏蔽层和多个肋。 屏蔽层形成在距导电圈的选定距离处。 屏蔽层被图案化成屏蔽部分以防止涡流。 多个肋由位于导电圈和屏蔽层之间的导电层形成。 每个肋电耦合到单个相关联的屏蔽部分。 此外，每个肋比其相关联的屏蔽部分更加导电，以提供比其相关联的屏蔽部分更小的电阻电流路径。

公开(公告)号：US20030173941A1

公开(公告)日：2003-09-18

申请号：US10100439

申请日：2002-03-18

Applicant: Intersil Americas Inc.

Inventor： Matthew Burdet Harris ,  Robert Haynes Isham

IPC: G05F001/40

CPC classification number: H02M3/156 ,  H02M3/1588 ,  H02M2003/1566 ,  Y02B70/1466

Abstract: A DC-to-DC converter includes a pulse width modulation (PWM) circuit cooperating with at least one power switch for supplying power from a source to a load over a range between a lower limit and an upper limit to thereby control an output voltage for the load. The converter may also include a primary feedback control loop cooperating with the PWM circuit for supplying power to the load between the lower and upper limits based upon the output voltage during normal load transient conditions. The converter may also include at least one override feedback control loop cooperating with the PWM circuit for overriding the primary feedback control loop and supplying power to the load at one of the lower and upper limits based upon the output voltage during a corresponding relatively fast load transient condition. Accordingly, relatively fast load transients can be followed by the converter.

Abstract translation: DC-DC转换器包括与至少一个功率开关配合的脉冲宽度调制（PWM）电路，用于在下限和上限之间的范围内从源向负载供电，从而控制输出电压 负载。 转换器还可以包括与PWM电路配合的主反馈控制回路，用于在正常负载瞬态条件期间基于输出电压向下限和上限之间的负载供电。 转换器还可以包括与PWM电路协作的至少一个覆盖反馈控制环路，用于覆盖主反馈控制回路，并且在相应的相对快速的负载瞬变期间基于输出电压在下限和上限中的一个处向负载供电 条件。 因此，转换器可以跟随相对较快的负载瞬变。

公开(公告)号：US20030157756A1

公开(公告)日：2003-08-21

申请号：US10365343

申请日：2003-02-12

Applicant: Intersil Americas Inc.

Inventor： James D. Beasom

IPC: H01L021/336

CPC classification number: H01L29/0878 ,  H01L29/0615 ,  H01L29/0847 ,  H01L29/0882 ,  H01L29/1087 ,  H01L29/7835

Abstract: An integrated circuit having a high voltage lateral MOS with reduced ON resistance. In one embodiment, the integrated circuit includes a high voltage lateral MOS with an island forned in a substrate, a source, a gate and a first and second drain extension. The island is doped with a low density first conductivity type. The source and drain contact are both doped with a high density second conductivity type. The first drain extension is of the second conductivity type and extends laterally from under the gate past the drain contact. The second drain extension is of the second conductivity type and extends laterally from under the gate toward the source. A portion of the second drain extension overlaps the first drain extension under the gate to form a region of increased doping of the second conductivity type.

Abstract translation: 具有降低的导通电阻的具有高电压横向MOS的集成电路。 在一个实施例中，集成电路包括高压横向MOS，其具有用于衬底的岛，源极，栅极以及第一和第二漏极延伸。 该岛掺杂有低密度第一导电类型。 源极和漏极接触均掺杂有高密度第二导电类型。 第一漏极延伸部是第二导电类型，并且从栅极下方横向延伸穿过漏极接触。 第二漏极延伸部是第二导电类型，并且从栅极下方向源极侧向延伸。 第二漏极延伸部分与栅极之下的第一漏极延伸部分重叠以形成第二导电类型的掺杂增加的区域。