公开(公告)号：US20040161905A1

公开(公告)日：2004-08-19

申请号：US10779121

申请日：2004-02-12

Applicant: Intersil Americas Inc.

Inventor： Joseph A. Czagas ,  Dustin A. Woodbury ,  James D. Beasom

IPC: H01L021/30

CPC classification number: H01L21/2253 ,  H01L21/187 ,  H01L21/2007 ,  H01L21/2255 ,  H01L21/2256 ,  H01L21/26513 ,  H01L21/74 ,  H01L21/76251 ,  H01L29/0615 ,  H01L29/10 ,  H01L29/1079 ,  H01L29/1083 ,  Y10S438/933

Abstract: Integrated circuits, semiconductor devices and methods for making the same are described. Each embodiment shows a diffused, doped backside layer in a device wafer that is oxide bonded to a handle wafer. The diffused layer may originate in the device handle, in the handle wafer, in the bond oxide or in an additional semiconductor layer of polysilicon or epitaxial silicon. The methods use a thermal bond oxide or a combination of a thermal and deposited oxide.

Abstract translation: 描述了集成电路，半导体器件及其制造方法。 每个实施例在装置晶片中示出了在处理晶片上氧化物结合的扩散的掺杂​​背面层。 扩散层可以源于器件手柄，处理晶片，粘合氧化物或多晶硅或外延硅的附加半导体层。 该方法使用热粘合氧化物或热和沉积氧化物的组合。

公开(公告)号：US20030096481A1

公开(公告)日：2003-05-22

申请号：US09990330

申请日：2001-11-21

Applicant: INTERSIL AMERICAS INC.

Inventor： James D. Beasom

IPC: H01L021/336

CPC classification number: H01L29/0847 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/402 ,  H01L29/66659 ,  H01L29/735 ,  H01L29/7835 ,  H01L29/8611 ,  H01L2924/0002 ,  H03K17/941 ,  H01L2924/00

Abstract: Apparatus and Methods for the self-alignment of separated regions in a lateral MOSFET of an integrate circuit. In one embodiment, a method comprising, forming a relatively thin dielectric layer on a surface of a substrate. Forming a first region of relatively thick material having a predetermined lateral length on the surface of the substrate adjacent the relatively thin dielectric layer. Implanting dopants to form a top gate using a first edge of the first region as a mask to define a first edge of the top gate. Implanting dopants to form a drain contact using a second edge of the first region as a mask to define a first edge of the drain contact, wherein the distance between the top gate and drain contact is defined by the lateral length of the first region.

Abstract translation: 用于集成电路的横向MOSFET中分离区域的自对准的装置和方法。 在一个实施例中，一种方法包括：在衬底的表面上形成相对薄的电介质层。 在相邻较薄的电介质层的基板的表面上形成具有预定横向长度的较厚材料的第一区域。 使用第一区域的第一边缘作为掩模将植入掺杂剂形成顶部栅极以限定顶部栅极的第一边缘。 使用第一区域的第二边缘作为掩模来植入掺杂剂以形成漏极接触，以限定漏极接触的第一边缘，其中顶部栅极和漏极接触之间的距离由第一区域的横向长度限定。

公开(公告)号：US20040159912A1

公开(公告)日：2004-08-19

申请号：US10366158

申请日：2003-02-13

Applicant: INTERSIL AMERICAS INC.

Inventor： James D. Beasom

IPC: H01L027/082

CPC classification number: H01L29/7304 ,  H01L27/0658 ,  H01L27/067

Abstract: An integrated circuit including a bipolar transistor with improved forward second breakdown is disclosed. In one embodiment, the bipolar transistor includes a base, a collector, a plurality of emitter sections coupled to a common emitter and a ballast emitter for each emitter section. Each ballast resistor is coupled between the common emitter and an associated emitter section. The size of each ballast resistor is selected so that the size of the ballast resistors vary across a two dimensional direction in relation to a lateral surface of the bipolar transistor.

Abstract translation: 公开了一种集成电路，其包括具有改进的向前二次击穿的双极晶体管。 在一个实施例中，双极晶体管包括基极，集电极，耦合到公共发射极的多个发射极部分和用于每个发射极部分的镇流发射极。 每个镇流电阻器耦合在公共发射极和相关的发射极部分之间。 选择每个镇流电阻器的尺寸，使得镇流电阻器的尺寸相对于双极晶体管的侧表面在二维方向上变化。

公开(公告)号：US20030080395A1

公开(公告)日：2003-05-01

申请号：US10033156

申请日：2001-10-25

Applicant: Intersil Americas Inc.

Inventor： James D. Beasom

IPC: H01L021/331 ,  H01L027/082 ,  H01L029/70 ,  H01L023/58 ,  H01L031/11

CPC classification number: H01L21/76802 ,  H01L21/3185

Abstract: The present invention relates to an integrated circuit having a sealed nitride layer. In one embodiment, a method of forming a sealing nitride layer overlaying a silicon oxide layer in a contact opening of an integrated circuit is disclosed. The method comprises, forming a second layer of nitride overlaying a first layer of nitride to form the sealing nitride layer. The second layer of nitride further overlays an exposed portion of a surface of a substrate in the contact opening and sidewalls of the contact opening. Using reactive ion etching (RIE etch) without a mask to remove a portion of the second nitride layer adjacent the surface of the substrate in the contact opening to expose a portion of the surface of the substrate in the contact opening without removing portions of the second nitride layer covering the sidewalls of the contact opening.

Abstract translation: 本发明涉及具有密封氮化物层的集成电路。 在一个实施例中，公开了一种在集成电路的接触开口中形成覆盖氧化硅层的密封氮化物层的方法。 该方法包括：形成覆盖第一氮化层的第二氮化物层以形成密封氮化物层。 第二层氮化物进一步覆盖接触开口中的基板的表面的暴露部分和接触开口的侧壁。 使用没有掩模的反应离子蚀刻（RIE蚀刻）去除接触开口中邻近衬底表面的第二氮化物层的一部分，以暴露接触开口中衬底表面的一部分，而不去除第二 覆盖接触开口的侧壁的氮化物层。

公开(公告)号：US20040180485A1

公开(公告)日：2004-09-16

申请号：US10811360

申请日：2004-03-26

Applicant: Intersil Americas Inc.

Inventor： James D. Beasom

IPC: H01L021/336 ,  H01L021/8234

CPC classification number: H01L29/7813 ,  H01L27/0921 ,  H01L29/1095 ,  H01L29/165 ,  H01L29/7801 ,  H01L29/7809 ,  H01L29/7835

Abstract: An integrated circuit having a MOS structure with reduced parasitic bipolar transistor action. In one embodiment, a MOS integrated circuit device comprises a substrate having a working surface, at least one body region and for each body region a source and a layer of narrow band gap material. Each body region is formed in the substrate proximate the working surface of the substrate. Each layer of narrow band gap material is positioned in a portion of its associated body region and proximate the working surface of the substrate. Each layer of narrow band gap material has a band gap that is narrower than the band gap of the substrate in which each of the body regions are formed. Each source region is formed in an associated body region. At least a portion of each source region is also formed in an associated layer of narrow band gap material.

公开(公告)号：US20030157756A1

公开(公告)日：2003-08-21

申请号：US10365343

申请日：2003-02-12

Applicant: Intersil Americas Inc.

Inventor： James D. Beasom

IPC: H01L021/336

CPC classification number: H01L29/0878 ,  H01L29/0615 ,  H01L29/0847 ,  H01L29/0882 ,  H01L29/1087 ,  H01L29/7835

Abstract: An integrated circuit having a high voltage lateral MOS with reduced ON resistance. In one embodiment, the integrated circuit includes a high voltage lateral MOS with an island forned in a substrate, a source, a gate and a first and second drain extension. The island is doped with a low density first conductivity type. The source and drain contact are both doped with a high density second conductivity type. The first drain extension is of the second conductivity type and extends laterally from under the gate past the drain contact. The second drain extension is of the second conductivity type and extends laterally from under the gate toward the source. A portion of the second drain extension overlaps the first drain extension under the gate to form a region of increased doping of the second conductivity type.

Abstract translation: 具有降低的导通电阻的具有高电压横向MOS的集成电路。 在一个实施例中，集成电路包括高压横向MOS，其具有用于衬底的岛，源极，栅极以及第一和第二漏极延伸。 该岛掺杂有低密度第一导电类型。 源极和漏极接触均掺杂有高密度第二导电类型。 第一漏极延伸部是第二导电类型，并且从栅极下方横向延伸穿过漏极接触。 第二漏极延伸部是第二导电类型，并且从栅极下方向源极侧向延伸。 第二漏极延伸部分与栅极之下的第一漏极延伸部分重叠以形成第二导电类型的掺杂增加的区域。

公开(公告)号：US20030087496A1

公开(公告)日：2003-05-08

申请号：US09992880

申请日：2001-11-05

Applicant: Intersil Americas Inc.

Inventor： James D. Beasom

IPC: H01L021/336

CPC classification number: H01L27/0658 ,  H01L21/31144 ,  H01L21/76802 ,  H01L27/067 ,  H01L27/0811

Abstract: The present invention relates to an integrated circuit having a MOS capacitor. In one embodiment, a method of forming an integrated circuit comprises forming an oxide layer on a surface of a substrate, the substrate having a plurality of isolation islands. Each isolation island is used in forming a semiconductor device. Patterning the oxide layer to expose predetermined areas of the surface of the substrate. Depositing a nitride layer overlaying the oxide layer and the exposed surface areas of the substrate. Implanting ions through the nitride layer, wherein the nitride layer is an implant screen for the implanted ions. Using the nitride layer as a capacitor dielectric in forming a capacitor. In addition, performing a dry etch to form contact openings that extend through the layer of nitride and through the layer of oxide to access selected device regions formed in the substrate.

Abstract translation: 本发明涉及具有MOS电容器的集成电路。 在一个实施例中，形成集成电路的方法包括在衬底的表面上形成氧化物层，所述衬底具有多个隔离岛。 每个隔离岛用于形成半导体器件。 对氧化物层进行构图以暴露衬底表面的预定区域。 沉积覆盖氧化物层的氮化物层和衬底的暴露的表面区域。 将离子注入氮化物层，其中氮化物层是用于注入离子的注入屏。 在形成电容器时使用氮化物层作为电容器电介质。 此外，进行干蚀刻以形成延伸穿过氮化物层并通过氧化物层的接触开口，以接触形成在衬底中的选定器件区域。

公开(公告)号：US20020185696A1

公开(公告)日：2002-12-12

申请号：US10104342

申请日：2002-03-22

Applicant: INTERSIL AMERICAS INC.

Inventor： James D. Beasom

IPC: H01L029/76

CPC classification number: H01L29/66659 ,  H01L29/0634 ,  H01L29/7816 ,  H01L29/7835

Abstract: A high voltage lateral semiconductor device for integrated circuits with improved breakdown voltage. The semiconductor device comprising a semiconductor body, an extended drain region formed in the semiconductor body, source and drain pockets, a top gate forming a pn junction with the extended drain region, an insulating layer on a surface of the semiconductor body and a gate formed on the insulating layer. In addition, a higher-doped pocket of semiconductor material is formed within the top gate region that has a higher integrated doping than the rest of the top gate region. This higher-doped pocket of semiconductor material does not totally deplete during device operation. Moreover, the gate controls, by field-effect, a flow of current through a channel formed laterally between the source pocket and a nearest point of the extended drain region.

Abstract translation: 具有改进的击穿电压的集成电路的高电压侧向半导体器件。 该半导体器件包括半导体本体，形成在半导体本体中的延伸漏极区，源极和漏极腔，形成与延伸漏极区的pn结的顶部栅极，半导体主体的表面上的绝缘层和形成的栅极 在绝缘层上。 此外，半导体材料的高掺杂阱形成在顶栅区内，其具有比顶栅区其余部分更高的集成掺杂。 这种较高掺杂的半导体材料袋在器件操作期间不会完全消耗。 此外，栅极通过场效应控制电流通过在源极袋和延伸的漏极区域的最近点之间横向形成的沟道。

公开(公告)号：US20030230789A1

公开(公告)日：2003-12-18

申请号：US10171349

申请日：2002-06-12

Applicant: INTERSIL AMERICAS INC.

Inventor： James D. Beasom

IPC: H01L027/082

CPC classification number: H01L29/6625 ,  H01L29/1004 ,  H01L29/1008 ,  H01L29/167 ,  H01L29/66272 ,  H01L29/7322 ,  H01L29/735

Abstract: An improved base for a NPN bipolar transistor. The base region is formed with Boron and Indium dopants for improved beta early voltage product and reduced base resistance.

Abstract translation: 改进的NPN双极晶体管基极。 碱性区域由硼和铟掺杂物形成，用于改进β早期电压产物和降低的碱电阻。

公开(公告)号：US20030178701A1

公开(公告)日：2003-09-25

申请号：US10360374

申请日：2003-02-06

Applicant: Intersil Americas Inc.

Inventor： James D. Beasom

IPC: H01L027/082 ,  H01L027/102 ,  H01L029/70 ,  H01L031/11

CPC classification number: H01L29/6659 ,  H01L21/2253 ,  H01L21/266 ,  H01L29/0692 ,  H01L29/0821 ,  H01L29/1079 ,  H01L29/7322

Abstract: In a semiconductor substrate having a top surface and a PN junction between a first region of one conductivity type formed by masked diffusion into a semiconductor from the surface and a second region of opposite conductivity type formed into a first portion of the first region from the surface, the improvement comprises one edge of the first region being spaced from the edge of the second region such that the doping concentration of the first region at the surface intersection of the four corners of the junction between the first and second regions is lower than it is at some other location in the region. A semiconductor device comprises; a substrate with a surface; a first region of one conductivity type that is defined by a first perimeter at the surface, extends from the surface to a first depth, and has a doping concentration that decrease with depth and with proximity to the first perimeter; and a second region of opposite conductivity type that is defined by a second perimeter, extends from the surface to a second depth, and has a doping concentration that decreases with depth and with proximity to the second perimeter. The second region overlaps the first region, and the doping concentration of the first region at the surface intersection of the first and second regions is less than the maximum doping concentration at other locations on the surface within the first perimeter where the second region overlaps the first region.

Abstract translation: 在半导体衬底中具有顶表面和PN结之间的一个导电类型的第一区域，该第一区域通过从表面被掩蔽扩散到半导体中而形成，第二区域相反导电型形成第一区域的第一部分， 改进包括第一区域的一个边缘与第二区域的边缘间隔开，使得第一区域和第二区域之间的结点的四个角的表面交叉处的第一区域的掺杂浓度低于第一区域 在该地区的其他地点。 半导体器件包括： 具有表面的基底; 由表面的第一周界限定的一种导电类型的第一区域从表面延伸到第一深度，并且具有随深度减小并且接近第一周边的掺杂浓度; 并且由第二周界限定的相反导电类型的第二区域从表面延伸到第二深度，并且具有随着深度和邻近第二周边而减小的掺杂浓度。 第二区域与第一区域重叠，并且第一和第二区域的表面交叉处的第一区域的掺杂浓度小于在第一周边内的表面上的其它位置处的最大掺杂浓度，其中第二区域与第一区域重叠 地区。