公开(公告)号：US20090286370A1

公开(公告)日：2009-11-19

申请号：US12510077

申请日：2009-07-27

申请人： Eliyahou Harari ,  George Samachisa ,  Jack H. Yuan ,  Daniel C. Guterman

发明人： Eliyahou Harari ,  George Samachisa ,  Jack H. Yuan ,  Daniel C. Guterman

IPC分类号： H01L21/336 ,  H01L21/8234 ,  H01L21/8239

CPC分类号： H01L27/11568 ,  B82Y10/00 ,  G11C11/5671 ,  G11C16/0466 ,  G11C16/0475 ,  G11C16/0483 ,  G11C16/0491 ,  G11C2216/06 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/4234 ,  H01L29/7923 ,  Y10S438/947

摘要： Non-volatile memory cells store a level of charge corresponding to the data being stored in a dielectric material storage element that is sandwiched between a control gate and the semiconductor substrate surface over channel regions of the memory cells. More than two memory states are provided by one of more than two levels of charge being stored in a common region of the dielectric material. More than one such common region may be included in each cell. In one form, two such regions are provided adjacent source and drain diffusions in a cell that also includes a select transistor positioned between them. In another form, NAND arrays of strings of memory cells store charge in regions of a dielectric layer sandwiched between word lines and the semiconductor substrate.

摘要翻译： 非易失性存储单元存储对应于存储在存储单元的沟道区上夹在控制栅极和半导体衬底表面之间的介电材料存储元件中的数据的电荷水平。 通过存储在电介质材料的公共区域中的多于两个的电荷中的一个来提供两个以上的记忆状态。 每个单元中可以包括多于一个这样的共同区域。 在一种形式中，在单元中邻近的源和漏扩散设置了两个这样的区域，该单元还包括位于它们之间的选择晶体管。 在另一种形式中，存储单元串的NAND阵列在夹在字线和半导体衬底之间的电介质层的区域中存储电荷。

公开(公告)号：US07402886B2

公开(公告)日：2008-07-22

申请号：US11251400

申请日：2005-10-14

申请人： Jack H. Yuan

发明人： Jack H. Yuan

IPC分类号： H01L29/00

CPC分类号： H01L27/11521 ,  H01L21/76205 ,  H01L21/76232 ,  H01L27/115

摘要： Self-aligned trench filling is used to isolate devices in high-density integrated circuits. A deep, narrow trench isolation region is formed in a substrate between devices. The trench region includes two trench portions. A first trench portion, located above a second trench portion, is filled with a deposited dielectric. The second trench portion is filled with a grown dielectric. Filling the lower trench portion by growing a dielectric material provides for an even distribution of dielectric material within the lower portion. Filling the upper trench portion by depositing a dielectric material provides for an even distribution of material in the upper portion while also protecting against encroachment of the dielectric into device channel regions, for example. Devices can be fabricated by etching the substrate to form the trench region after or as part of etching one or more layers formed above the substrate for the device. This can ensure alignment of the gate and channel regions of a device between trench isolation regions.

摘要翻译： 自对准沟槽填充用于隔离高密度集成电路中的器件。 在器件之间的衬底中形成深而窄的沟槽隔离区域。 沟槽区域包括两个沟槽部分。 位于第二沟槽部分上方的第一沟槽部分填充有沉积的电介质。 第二沟槽部分填充有生长的电介质。 通过生长电介质材料填充下沟槽部分提供在下部分内的电介质材料的均匀分布。 通过沉积介电材料来填充上沟槽部分提供了在上部分中材料的均匀分布，同时还防止例如电介质侵入器件沟道区域。 可以通过蚀刻衬底来形成器件，以在蚀刻形成在器件的衬底上方的一个或多个层之后或部分地形成沟槽区域。 这可以确保器件在沟槽隔离区域之间的栅极和沟道区域的对准。

公开(公告)号：US07087951B2

公开(公告)日：2006-08-08

申请号：US10848242

申请日：2004-05-17

申请人： Eliyahou Harari ,  Jack H. Yuan ,  George Samachisa ,  Henry Chien

发明人： Eliyahou Harari ,  Jack H. Yuan ,  George Samachisa ,  Henry Chien

IPC分类号： H01L29/76

CPC分类号： H01L27/11521 ,  G11C16/0416 ,  H01L27/115 ,  H01L27/11553

摘要： Several embodiments of flash EEPROM split-channel cell arrays are described that position the channels of cell select transistors along sidewalls of trenches in the substrate, thereby reducing the cell area. Select transistor gates are formed as part of the word lines and extend downward into the trenches with capacitive coupling between the trench sidewall channel portion and the select gate. In one embodiment, trenches are formed between every other floating gate along a row, the two trench sidewalls providing the select transistor channels for adjacent cells, and a common source/drain diffusion is positioned at the bottom of the trench. A third gate provides either erase or steering capabilities. In another embodiment, trenches are formed between every floating gate along a row, a source/drain diffusion extending along the bottom of the trench and upwards along one side with the opposite side of the trench being the select transistor channel for a cell. In another embodiment, select transistor gates of dual floating gate memory cells are extended into trenches or recesses in the substrate in order to lengthen the select transistor channel as the surface dimensions of the cell are being decreased. Techniques for manufacturing such flash EEPROM split-channel cell arrays are also included.

公开(公告)号：US06936887B2

公开(公告)日：2005-08-30

申请号：US09925134

申请日：2001-08-08

申请人： Eliyahou Harari ,  Jack H. Yuan ,  George Samachisa ,  Henry Chien

发明人： Eliyahou Harari ,  Jack H. Yuan ,  George Samachisa ,  Henry Chien

IPC分类号： H01L27/10 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L27/11521 ,  G11C16/0416 ,  H01L27/115 ,  H01L27/11553

摘要： Several embodiments of flash EEPROM split-channel cell arrays are described that position the channels of cell select transistors along sidewalls of trenches in the substrate, thereby reducing the cell area. Select transistor gates are formed as part of the word lines and extend downward into the trenches with capacitive coupling between the trench sidewall channel portion and the select gate. In one embodiment, trenches are formed between every other floating gate along a row, the two trench sidewalls providing the select transistor channels for adjacent cells, and a common source/drain diffusion is positioned at the bottom of the trench. A third gate provides either erase or steering capabilities. In another embodiment, trenches are formed between every floating gate along a row, a source/drain diffusion extending along the bottom of the trench and upwards along one side with the opposite side of the trench being the select transistor channel for a cell. In another embodiment, select transistor gates of dual floating gate memory cells are extended into trenches or recesses in the substrate in order to lengthen the select transistor channel as the surface dimensions of the cell are being decreased. Techniques for manufacturing such flash EEPROM split-channel cell arrays are also included.

摘要翻译： 描述了闪存EEPROM分离通道单元阵列的几个实施例，其将单元选择晶体管的通道定位在衬底中的沟槽的侧壁，从而减小单元面积。 选择晶体管栅极形成为字线的一部分，并且通过沟槽侧壁沟道部分和选择栅极之间的电容耦合向下延伸到沟槽中。 在一个实施例中，在沿着一行的每隔一个浮置栅极之间形成沟槽，两个沟槽侧壁为相邻电池提供选择晶体管沟道，并且公共源极/漏极扩散部位于沟槽的底部。 第三个门提供擦除或转向功能。 在另一个实施例中，在沿着一排的每个浮置栅极之间形成沟槽，沿沟槽的底部延伸的源极/漏极扩散器和沿着一侧的向上并且沟槽的相对侧为用于电池的选择晶体管沟道。 在另一个实施例中，双浮置栅极存储器单元的选择晶体管栅极延伸到衬底中的沟槽或凹槽中，以便随着单元的表面尺寸减小而延长选择晶体管沟道。 还包括用于制造这种快速EEPROM分离通道单元阵列的技术。

公开(公告)号：US06908817B2

公开(公告)日：2005-06-21

申请号：US10268635

申请日：2002-10-09

申请人： Jack H. Yuan

发明人： Jack H. Yuan

IPC分类号： H01L21/8247 ,  H01L27/115 ,  H01L29/423 ,  H01L21/336

CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L27/11526 ,  H01L27/11543 ,  H01L29/42324 ,  H01L29/66825 ,  H01L29/7881

摘要： Floating gate structures are disclosed which have a base field coupled with the substrate and a narrow projection extending from the base away from the substrate. In one form, surfaces of a relatively large projection provide an increased surface area for a control gate that wraps around it, thereby increasing the coupling between the two. In another form, an erase gate wraps around a relatively small projection in order to take advantage of sharp edges of the projection to promote tunneling of electrons from the floating to the erase gate. In each case, the control or floating gate is positioned within the area of the floating gate in one direction, thereby not requiring additional substrate area for such memory cells.

摘要翻译： 公开了浮动栅极结构，其具有与基底耦合的基极区域和从基底远离基底延伸的窄突起。 在一种形式中，相对大的突起的表面为包围其的控制栅提供增加的表面积，从而增加两者之间的耦合。 在另一种形式中，擦除栅极围绕相对较小的突起卷绕，以便利用突起的尖锐边缘来促进电子从浮动栅极到擦除栅极的隧穿。 在每种情况下，控制或浮动栅极在一个方向上位于浮动栅极的区域内，从而不需要这种存储器单元的附加衬底区域。

公开(公告)号：US06897522B2

公开(公告)日：2005-05-24

申请号：US10002696

申请日：2001-10-31

申请人： Eliyahou Harari ,  George Samachisa ,  Jack H. Yuan ,  Daniel C. Guterman

发明人： Eliyahou Harari ,  George Samachisa ,  Jack H. Yuan ,  Daniel C. Guterman

IPC分类号： G11C11/56 ,  G11C16/04 ,  H01L21/8246 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L27/11568 ,  B82Y10/00 ,  G11C11/5671 ,  G11C16/0466 ,  G11C16/0475 ,  G11C16/0483 ,  G11C16/0491 ,  G11C2216/06 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/4234 ,  H01L29/7923

摘要： Non-volatile memory cells store a level of charge corresponding to the data being stored in a dielectric material storage element that is sandwiched between a control gate and the semiconductor substrate surface over channel regions of the memory cells. More than two memory states are provided by one of more than two levels of charge being stored in a common region of the dielectric material. More than one such common region may be included in each cell. In one form, two such regions are provided adjacent source and drain diffusions in a cell that also includes a select transistor positioned between them.

摘要翻译： 非易失性存储单元存储对应于存储在存储单元的沟道区上夹在控制栅极和半导体衬底表面之间的介电材料存储元件中的数据的电荷水平。 通过存储在电介质材料的公共区域中的多于两个的电荷中的一个来提供两个以上的记忆状态。 每个单元中可以包括多于一个这样的共同区域。 在一种形式中，在单元中邻近的源和漏扩散设置了两个这样的区域，该单元还包括位于它们之间的选择晶体管。

公开(公告)号：US06723604B2

公开(公告)日：2004-04-20

申请号：US10265066

申请日：2002-10-03

申请人： Jack H. Yuan ,  Jacob Haskell

发明人： Jack H. Yuan ,  Jacob Haskell

IPC分类号： H01L21336

CPC分类号： H01L27/11521 ,  G11C16/0416 ,  G11C16/0458 ,  H01L27/115 ,  H01L27/11524 ,  H01L29/66825 ,  H01L29/7887

摘要： Rows of memory cells are electrically isolated from one another by trenches formed in the substrate between the rows that are filled with a dielectric, commonly called “shallow trench isolation” or “STI.” Discontinuous source and drain regions of the cells are connected together by column oriented bit lines, preferably made of doped polysilicon, that extend in the column direction on top of the substrate. This structure is implemented in a flash memory array of cells having either one floating gate per cell or at least two floating gates per cell. A process of making a dual-floating gate memory cell array includes etching the word lines twice along their lengths, once to form openings through which source and drain implants are made and in which the conductive bit lines are formed, and second to form individual floating gates with a select transistor gate positioned between them that also serves to erase charge from the adjacent floating gates.

公开(公告)号：US06420231B1

公开(公告)日：2002-07-16

申请号：US09613640

申请日：2000-07-11

申请人： Eliyahou Harari ,  Jack H. Yuan ,  George Samachisa

发明人： Eliyahou Harari ,  Jack H. Yuan ,  George Samachisa

IPC分类号： H01L21336

CPC分类号： H01L27/11521 ,  H01L29/66825 ,  H01L29/7887

摘要： An EEPROM system having an array of memory cells that individually include two floating gates, bit line source and drain diffusions extending along columns, steering gates also extending along columns and select gates forming word lines along rows of floating gates. The dual gate cell increases the density of data that can be stored. Rather than providing a separate steering gate for each column of floating gates, an individual steering gate is shared by two adjacent columns of floating gates that have a diffusion between them. Processing methods of forming such a cell array include two etching steps to separate strips of conductive material into individual floating gates that are self-aligned with source/drain diffusions and other gate elements. In one embodiment, this is accomplished by two etching steps with separate masks. In another embodiment, a reference dielectric mask is first formed over the conductive material layer strips and used as a reference for two etching masks that are aligned with each other. In a further embodiment, isolation of the memory cells is provided in the column direction by forming rectangular trenches in the substrate between cells that are filled with dielectric. Specific processing techniques also have applications to form single floating gate EEPROM cell arrays, other types of memory cells and integrated circuit elements.

摘要翻译： 具有存储单元阵列的EEPROM系统，其独立地包括两个浮动栅极，沿列延伸的位线源极和漏极扩散，还沿着列延伸的转向栅极以及沿着浮动栅极行沿着形成字线的选择栅极。 双门单元增加了可以存储的数据的密度。 不是为每列浮动栅栏提供单独的转向门，而是由两个相邻的悬浮门之间共享一个单独的转向门，这两个浮动门在它们之间具有扩散。 形成这种单元阵列的处理方法包括两个蚀刻步骤，以将导电材料的条带分离成与源极/漏极扩散和其它栅极元件自对准的各自的浮置栅极。 在一个实施例中，这通过具有分开的掩模的两个蚀刻步骤来实现。 在另一个实施例中，首先在导电材料层条上形成参考电介质掩模，并将其用作彼此对准的两个蚀刻掩模的参考。 在另一实施例中，通过在填充有电介质的单元之间的衬底中形成矩形沟槽，在列方向上提供存储单元的隔离。 具体的处理技术也具有形成单个浮置栅极EEPROM单元阵列，其它类型的存储单元和集成电路元件的应用。

公开(公告)号：US06344993B1

公开(公告)日：2002-02-05

申请号：US09904945

申请日：2001-07-13

申请人： Eliyahou Harari ,  Daniel C. Guterman ,  George Samachisa ,  Jack H. Yuan

发明人： Eliyahou Harari ,  Daniel C. Guterman ,  George Samachisa ,  Jack H. Yuan

IPC分类号： G11C1604

CPC分类号： G11C16/0475 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5635 ,  G11C11/5642 ,  G11C16/0458 ,  G11C2211/5612 ,  H01L27/115

摘要： An EEPROM system having an array of memory cells that individually include two floating gates, bit line source and drain diffusions extending along columns, steering gates also extending along columns and select gates forming word lines along rows of floating gates. The dual gate cell increases the density of data that can be stored. Rather than providing a separate steering gate for each column of floating gates, an individual steering gate is shared by two adjacent columns of floating gates that have a diffusion between them. The steering gate is thus shared by two floating gates of different but adjacent memory cells. In one array embodiment, the floating gates are formed on the surface of the substrate, where the added width of the steering gates makes them easier to form, removes them as a limitation upon scaling the array smaller, require fewer electrical contacts along their length because of increased conductance, are easier to contact, and reduces the number of conductive traces that are needed to connect with them. In arrays that erase the floating gates to the select gates, rather than to the substrate, the wider steering gates advantageously uncouple the diffusions they cover from the select gates. This use of a single steering gate for two floating gates also allows the floating gates, in another embodiment, to be formed on side walls of trenches in the substrate with the common steering gate between them, to further increase the density of data that can be stored. Multiple bits of data can also be stored on each floating gate.

摘要翻译： 具有存储单元阵列的EEPROM系统，其独立地包括两个浮动栅极，沿列延伸的位线源极和漏极扩散，还沿着列延伸的转向栅极以及沿着浮动栅极行沿着形成字线的选择栅极。 双门单元增加了可以存储的数据的密度。 不是为每列浮动栅栏提供单独的转向门，而是由两个相邻的悬浮门之间共享一个单独的转向门，这两个浮动门在它们之间具有扩散。 因此，转向门由不同但相邻的存储单元的两个浮动门共享。 在一个阵列实施例中，浮动栅极形成在基板的表面上，其中增加的转向门的宽度使得它们更容易形成，作为对阵列的缩小的限制，将它们移除，因为它们的尺寸较小，因此需要更少的沿着它们的长度的电触点，因为 增加电导，更容易接触，并减少与它们连接所需的导电迹线的数量。 在将浮动栅极擦除到选择栅极而不是衬底的阵列中，较宽的转向栅极有利地使其从选择栅极覆盖的扩散分离。 单个转向门用于两个浮动栅极的这种使用也允许浮动栅极在另一个实施例中形成在衬底中的沟槽的侧壁上，其间具有公共转向栅极，以进一步增加数据的密度 存储。 多个数据位也可以存储在每个浮动门上。

公开(公告)号：US6151248A

公开(公告)日：2000-11-21

申请号：US343328

申请日：1999-06-30

申请人： Eliyahou Harari ,  Daniel C. Guterman ,  George Samachisa ,  Jack H. Yuan

发明人： Eliyahou Harari ,  Daniel C. Guterman ,  George Samachisa ,  Jack H. Yuan

IPC分类号： G11C11/56 ,  G11C16/04 ,  H01L27/115

CPC分类号： G11C16/0475 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5635 ,  G11C11/5642 ,  G11C16/0458 ,  H01L27/115 ,  G11C2211/5612

摘要： An EEPROM system having an array of memory cells that individually include two floating gates, bit line source and drain diffusions extending along columns, steering gates also extending along columns and select gates forming word lines along rows of floating gates. The dual gate cell increases the density of data that can be stored. Rather than providing a separate steering gate for each column of floating gates, an individual steering gate is shared by two adjacent columns of floating gates that have a diffusion between them. The steering gate is thus shared by two floating gates of different but adjacent memory cells. In one array embodiment, the floating gates are formed on the surface of the substrate, where the added width of the steering gates makes them easier to form, removes them as a limitation upon scaling the array smaller, require fewer electrical contacts along their length because of increased conductance, are easier to contact, and reduces the number of conductive traces that are needed to connect with them. In arrays that erase the floating gates to the select gates, rather than to the substrate, the wider steering gates advantageously uncouple the diffusions they cover from the select gates. This use of a single steering gate for two floating gates also allows the floating gates, in another embodiment, to be formed on side walls of trenches in the substrate with the common steering gate between them, to further increase the density of data that can be stored. Multiple bits of data can also be stored on each floating gate.