公开(公告)号：US20080056006A1

公开(公告)日：2008-03-06

申请号：US11642925

申请日：2006-12-21

Applicant: Kee-Ho Jung ,  Jae-Yong Jeong ,  Chi-Weon Yoon

Inventor： Kee-Ho Jung ,  Jae-Yong Jeong ,  Chi-Weon Yoon

IPC: G11C11/34

CPC classification number: G11C11/5628 ,  G11C16/3454 ,  G11C16/3459 ,  G11C2211/5621

Abstract: A method for programming a flash memory device is provided, where the flash memory device includes a plurality of memory cells, and where a threshold voltage of each of the memory cells is programmable in any one of plural corresponding data states. The method includes programming selected memory cells in a first data state, verifying a result of the programming, successively programming selected memory cells in at least two or more data states corresponding to threshold voltages which are lower than a corresponding threshold voltage of the first data state, and verifying results of the successive programming

Abstract translation: 提供一种用于对闪速存储器件进行编程的方法，其中闪速存储器件包括多个存储器单元，并且其中每个存储器单元的阈值电压可以以多个对应的数据状态中的任何一个来编程。 该方法包括以第一数据状态编程所选择的存储器单元，验证编程结果，以对应于低于第一数据状态的对应阈值电压的阈值电压的至少两个或多个数据状态连续地编程所选择的存储器单元 ，并验证连续编程的结果

公开(公告)号：US20070280003A1

公开(公告)日：2007-12-06

申请号：US11598788

申请日：2006-11-14

Applicant: Jong In Choi ,  Jae Yong Jeong

Inventor： Jong In Choi ,  Jae Yong Jeong

IPC: G11C11/34 ,  G11C16/06 ,  G11C16/04

CPC classification number: G11C16/16 ,  G11C16/04 ,  G11C16/344 ,  G11C29/02 ,  G11C29/021 ,  G11C29/028

Abstract: A non-volatile semiconductor memory device comprises a plurality of memory sectors arranged in different memory banks having different bulk regions. The memory cells can be erased using a first mode erase operation, which determines different erase pass voltages for the respective memory sectors by successively increasing a bank voltage applied to each sector until the number of failed cells in each sector falls below a first failed cell threshold value, and a second mode erase operation, which applies the different erase pass voltages to the respective memory sectors for successively increasing periods of time until the number of failed cells in each sector falls below a second failed cell threshold value.

Abstract translation: 非易失性半导体存储器件包括布置在具有不同体积区域的不同存储体中的多个存储器扇区。 可以使用第一模式擦除操作来擦除存储器单元，该第一模式擦除操作通过连续增加施加到每个扇区的存储体电压来确定各个存储器扇区的不同擦除通过电压，直到每个扇区中的故障单元的数量低于第一故障单元阈值 值和第二模式擦除操作，其将不同的擦除遍电压施加到各个存储器扇区，用于连续增加的时间段，直到每个扇区中的故障小区的数量低于第二故障小区阈值。

公开(公告)号：US07266029B2

公开(公告)日：2007-09-04

申请号：US11017335

申请日：2004-12-20

Applicant: Jae-Yong Jeong

Inventor： Jae-Yong Jeong

IPC: G11C7/02

CPC classification number: G11C16/3436

Abstract: Data verification methods and/or nonvolatile memory devices are provided that concurrently detect data for a selected memory cell of the nonvolatile memory device and verify a programmed or erase state of previously detected data of a different memory cell of the nonvolatile memory device. Concurrently detecting data and verifying a programmed or erase state may be provided by a sense amplifier configured to sense data from a memory cell of the nonvolatile memory device, a latch configured to store the data sensed by the sense amplifier, an I/O buffer configured to store the data stored in the latch and a program/erase verifier circuit configured to control the sense amplifier, latch and I/O buffer to provided previously sensed data for a first memory cell to the program erase/verifier circuit for verification while the sense amplifier is sensing data for a second memory cell.

Abstract translation: 提供了数据验证方法和/或非易失性存储器件，其同时检测非易失性存储器件的选定存储单元的数据，并验证非易失性存储器件的不同存储单元的先前检测到的数据的编程或擦除状态。 同时检测数据和验证编程或擦除状态可以由配置成感测来自非易失性存储器件的存储单元的数据的读出放大器提供，配置成存储读出放大器检测到的数据的锁存器，配置的I / O缓冲器 存储在锁存器中的数据和编程/擦除验证器电路，其被配置为控制读出放大器，锁存器和I / O缓冲器，以将第一存储器单元的先前检测到的数据提供给程序擦除/验证器电路以进行验证 放大器感测第二存储单元的数据。

公开(公告)号：US20070035994A1

公开(公告)日：2007-02-15

申请号：US11453991

申请日：2006-06-16

Applicant: Jae-Phil Kong ,  Jae-Yong Jeong

Inventor： Jae-Phil Kong ,  Jae-Yong Jeong

IPC: G11C16/04 ,  G11C11/34

CPC classification number: G11C16/102 ,  G11C11/5628 ,  G11C2211/5621

Abstract: A method of programming a selected cell in a multi-level flash memory device comprises determining whether to program an upper bit or a lower bit of a selected memory cell, detecting a current logic state of two bits of data stored in the selected memory cell, determining a target logic state for the upper or lower bit, generating a program voltage and a verify voltage for programming the upper or lower bit to the target logic state, and applying the program voltage and the verify voltage to a word line connected to the selected memory cell.

Abstract translation: 一种在多级闪速存储器件中对所选单元进行编程的方法包括：确定是否编程所选存储单元的高位或低位，检测存储在所选存储单元中的两位数据的当前逻辑状态， 确定上位或下位的目标逻辑状态，产生用于将上位或下位编程为目标逻辑状态的编程电压和验证电压，以及将编程电压和验证电压施加到连接到所选择的字线的字线 记忆单元

公开(公告)号：US20060114725A1

公开(公告)日：2006-06-01

申请号：US11133234

申请日：2005-05-20

Applicant: Jae-Yong Jeong ,  Young-Ho Lim

Inventor： Jae-Yong Jeong ,  Young-Ho Lim

IPC: G11C16/04

CPC classification number: G11C16/3409 ,  G11C16/16 ,  G11C16/3404 ,  G11C16/344 ,  G11C16/3445

Abstract: Disclosed is a non-volatile memory device and a method of erasing the non-volatile memory device. An erase voltage is simultaneously applied to a plurality of sectors contained in the non-volatile memory device. Then, erase validation is sequentially performed for each of the plurality sectors and results of the erase validation are stored in a plurality of pass information registers. According to the results stored in the pass information registers, sectors which were not successfully erased are simultaneously re-erased and then sequentially re-validated until no such “failed sectors” remain in the non-volatile memory device. Upon eliminating the “failed sectors” from the non-volatile memory device, a post-program operation is sequentially performed on each of the plurality of sectors.

Abstract translation: 公开了一种非易失性存储器件和擦除非易失性存储器件的方法。 同时将擦除电压施加到包含在非易失性存储器件中的多个扇区。 然后，针对多个扇区中的每一个依次执行擦除验证，并将擦除确认的结果存储在多个通过信息寄存器中。 根据存储在通过信息寄存器中的结果，同时重新擦除未成功擦除的扇区，然后顺序重新验证，直到在非易失性存储器件中不存在这样的“故障扇区”为止。 在从非易失性存储器件消除“故障扇区”时，对多个扇区中的每一个依次执行后编程操作。

公开(公告)号：US20060098491A1

公开(公告)日：2006-05-11

申请号：US11265279

申请日：2005-11-03

Applicant: Jae-Yong Jeong ,  Young-Ho Lim

Inventor： Jae-Yong Jeong ,  Young-Ho Lim

IPC: G11C11/34 ,  G11C16/06

CPC classification number: G11C16/3459 ,  G11C16/12

Abstract: Disclosed is a non-volatile memory device and a method of programming the same. The non-volatile memory device comprises a plurality of memory cells that are programmed by supplying first and second program voltages thereto. In cases where the second program voltage rises above a predetermined detection voltage, the first program voltage is prevented from being supplied to the memory cell until the second program voltage falls below the detection voltage.

Abstract translation: 公开了一种非易失性存储器件及其编程方法。 非易失性存储器件包括通过向其提供第一和第二编程电压而被编程的多个存储器单元。 在第二编程电压升高到高于预定检测电压的情况下，防止第一编程电压被提供给存储单元，直到第二编程电压下降到检测电压以下。

公开(公告)号：US20060087889A1

公开(公告)日：2006-04-27

申请号：US11133286

申请日：2005-05-20

Applicant: Jae-yong Jeong

Inventor： Jae-yong Jeong

IPC: G11C16/04

CPC classification number: G11C16/102 ,  G11C16/30

Abstract: A method of programming a non-volatile memory device includes activating a first pump to generate a bitline voltage, and after the bulk voltage reaches a target voltage, detecting whether the bitline voltage is less than a detection voltage. When the bitline voltage is less than the detection voltage, a second pump becomes active.

Abstract translation: 一种编程非易失性存储器件的方法包括激活第一泵以产生位线电压，并且在体电压达到目标电压之后，检测位线电压是否小于检测电压。 当位线电压小于检测电压时，第二个泵变为有效。

公开(公告)号：US20060004970A1

公开(公告)日：2006-01-05

申请号：US10982560

申请日：2004-11-05

Applicant: Jae-Yong Jeong ,  Heung-soo Lim

Inventor： Jae-Yong Jeong ,  Heung-soo Lim

IPC: G06F12/00

CPC classification number: G11C16/10 ,  G11C16/30

Abstract: A nonvolatile memory device includes a memory cell array, a data scanning unit, and a program unit. The memory cell array includes a plurality of memory cells, where each of the memory cells is programmable to store data have a first logic value or a second logic value. The data scanning unit is configured to search among a plurality of data to be programmed in the memory cells to identify data having the second logic value. The program unit is configured to group the identified data having the second logic value, and to program at least a portion of the group of identified data at a same time into the memory cells.

Abstract translation: 非易失性存储器件包括存储单元阵列，数据扫描单元和程序单元。 存储单元阵列包括多个存储单元，其中每个存储器单元可编程以存储数据具有第一逻辑值或第二逻辑值。 数据扫描单元被配置为在存储器单元中要编程的多个数据之间搜索以识别具有第二逻辑值的数据。 程序单元被配置为对具有第二逻辑值的识别数据进行分组，并且将同一组的识别数据的至少一部分同时编程到存储器单元中。

公开(公告)号：US06891754B2

公开(公告)日：2005-05-10

申请号：US10927716

申请日：2004-08-27

Applicant: Jae-Yong Jeong ,  Sung-Soo Lee

Inventor： Jae-Yong Jeong ,  Sung-Soo Lee

IPC: G11C16/02 ,  G11C16/04 ,  G11C16/06 ,  G11C16/10 ,  G11C16/24 ,  G11C7/00

CPC classification number: G11C16/24 ,  G11C16/0483 ,  G11C16/10

Abstract: The invention provides a method of programming in a nonvolatile semiconductor memory device, having a plurality of memory cell strings connected to a plurality of bitlines and constructed of a plurality of memory cell transistors whose gates are coupled to a plurality of wordlines, and a plurality of registers corresponding to the bitlines. The method involves applying a first voltage to a first one of the bitlines and applying a second voltage to a second one of the bitline, the first bitline being adjacent to the second bitline, the first and second voltages being supplied from the registers; electrically isolating the first and second bitlines from their corresponding registers; charging the first bitline up to a third voltage higher than the first voltage and lower than the second voltage; and applying a fourth voltage to a wordline after cutting off current paths into the first and second bitlines.

公开(公告)号：US06807098B2

公开(公告)日：2004-10-19

申请号：US10659634

申请日：2003-09-09

Applicant: Jae-Yong Jeong ,  Sung-Soo Lee

Inventor： Jae-Yong Jeong ,  Sung-Soo Lee

IPC: G11C1604

CPC classification number: G11C16/24 ,  G11C16/0483 ,  G11C16/10

Abstract: The invention provides a method of programming in a nonvolatile semiconductor memory device, having a plurality of memory cell strings connected to a plurality of bitlines and constructed of a plurality of memory cell transistors whose gates are coupled to a plurality of wordlines, and a plurality of registers corresponding to the bitlines. The method involves applying a first voltage to a first one of the bitlines and applying a second voltage to a second one of the bitline, the first bitline being adjacent to the second bitline, the first and second voltages being supplied from the registers; electrically isolating the first and second bitlines from their corresponding registers; charging the first bitline up to a third voltage higher than the first voltage and lower than the second voltage; and applying a fourth voltage to a wordline after cutting off current paths into the first and second bitlines.