公开(公告)号：US20120051113A1

公开(公告)日：2012-03-01

申请号：US12945120

申请日：2010-11-12

Applicant: Min-Seok CHOI ,  Jong-Chern Lee

Inventor： Min-Seok CHOI ,  Jong-Chern Lee

IPC: G11C5/02 ,  G11C5/06 ,  H01L21/50

CPC classification number: H01L25/0657 ,  G11C5/025 ,  G11C5/04 ,  G11C5/063 ,  G11C29/12 ,  H01L2225/06541 ,  H01L2225/06596 ,  H01L2924/0002 ,  H01L2924/1434 ,  H01L2924/00

Abstract: A semiconductor integrated circuit includes a plurality of slave chips each including a core area including a memory cell array, a global data line configured to transfer input/output data of the corresponding core area, and a first peripheral circuit area configured to interface the corresponding core area and the corresponding global data line, a plurality of data transfer through-chip vias vertically formed through the plurality of slave chips, respectively, and coupled to the respective global data lines of the slave chips, and a master chip including a second peripheral circuit area configured to provide an input/output interface between the data transfer through-chip vias and an external controller.

Abstract translation: 半导体集成电路包括多个从芯片，每个从芯片包括包括存储单元阵列的核心区域，被配置为传送相应核心区域的输入/输出数据的全局数据线以及被配置为将对应的核心 区域和对应的全局数据线，分别通过多个从芯片垂直形成并耦合到从芯片的相应全局数据线的多个数据传输通过芯片通孔，以及包括第二外围电路的主芯片 区域被配置为在数据传送片上通孔和外部控制器之间提供输入/输出接口。

公开(公告)号：US20120049361A1

公开(公告)日：2012-03-01

申请号：US12980828

申请日：2010-12-29

Applicant: Byoung-Kwon PARK ,  Jong-Chern Lee

Inventor： Byoung-Kwon PARK ,  Jong-Chern Lee

IPC: H01L23/485 ,  H01L21/50

CPC classification number: H01L25/0657 ,  G11C5/025 ,  H01L23/147 ,  H01L23/50 ,  H01L2224/13014 ,  H01L2224/13021 ,  H01L2224/13023 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/1607 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06565 ,  H01L2924/14 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/00014

Abstract: A semiconductor integrated circuit includes a semiconductor chip including a memory cell array, a plurality of first through-chip vias configured to vertically penetrate through the semiconductor chip and operate as an interface for a signal and a supply voltage, and a semiconductor substrate. The semiconductor substrate includes a peripheral circuit region coupled to the plurality of first through-chip vias and configured to control the semiconductor chip and a conductivity pattern region configured to operate as an interface for the signal and the supply voltage between the peripheral circuit region and an external controller.

Abstract translation: 半导体集成电路包括：半导体芯片，包括存储单元阵列;多个第一贯通芯片通孔，其被配置为垂直穿过半导体芯片并作为信号和电源电压的接口进行操作;以及半导体衬底。 半导体衬底包括耦合到多个第一通孔的外围电路区域，并被配置为控制半导体芯片和导电图案区域，其被配置为作为信号的接口和外围电路区域与外部电路区域之间的电源电压 外部控制器

公开(公告)号：US20120007624A1

公开(公告)日：2012-01-12

申请号：US12914424

申请日：2010-10-28

Applicant: Sang-Jin Byeon ,  Jong-Chern Lee

Inventor： Sang-Jin Byeon ,  Jong-Chern Lee

IPC: G01R31/26

CPC classification number: G11C11/4072 ,  G06F2213/0038 ,  G11C7/10 ,  G11C8/12 ,  G11C11/4076 ,  G11C16/20

Abstract: A semiconductor system for identifying stacked chips includes a first semiconductor chip and a plurality of second semiconductor chips. The first semiconductor chip generates a plurality of counter codes by using an internal clock or an external input clock and transmits slave address signals and the counter codes through a through-chip via. The second semiconductor chips are given corresponding identifications (IDs) by latching the counter codes for a predetermined delay time, compare the latched counter codes with the slave address signals, and communicate data with the first semiconductor chip through the through-chip via according to the comparison result.

Abstract translation: 用于识别堆叠芯片的半导体系统包括第一半导体芯片和多个第二半导体芯片。 第一半导体芯片通过使用内部时钟或外部输入时钟产生多个计数器代码，并且通过片上通孔发送从地址信号和计数器代码。 通过在预定的延迟时间内锁存计数器代码来对第二半导体芯片进行相应的标识（ID），将锁存的计数器代码与从地址信号进行比较，并根据通过芯片通过与第一半导体芯片通信数据 比较结果。

公开(公告)号：US20110291730A1

公开(公告)日：2011-12-01

申请号：US12832549

申请日：2010-07-08

Applicant: Seung-Joon Ahn ,  Jong-Chern Lee

Inventor： Seung-Joon Ahn ,  Jong-Chern Lee

IPC: H03H11/26

CPC classification number: H03K5/135 ,  H03K2005/00104

Abstract: An open loop type delay locked loop includes a delay amount pulse generation unit configured to generate a delay amount pulse having a pulse width corresponding to a delay amount for delay locking a clock signal, a delay amount coding unit configured to output a code value by coding the delay amount in response to the delay amount pulse, a clock control unit configured to adjust a toggling period of the clock signal in response to a control signal, and a delay line configured to delay an adjusted clock signal outputted from the clock control unit in response to the code value.

Abstract translation: 开环型延迟锁定环包括：延迟量脉冲生成单元，被配置为生成具有对应于用于延迟锁定时钟信号的延迟量的脉冲宽度的延迟量脉冲;延迟量编码单元，被配置为通过编码输出代码值 延迟量响应于延迟量脉冲，时钟控制单元，被配置为响应于控制信号调整时钟信号的切换周期;以及延迟线，被配置为将从时钟控制单元输出的经调整的时钟信号延迟 响应代码值。

公开(公告)号：US20110188331A1

公开(公告)日：2011-08-04

申请号：US12839297

申请日：2010-07-19

Applicant: Sin Hyun JIN ,  Jong Chern Lee

Inventor： Sin Hyun JIN ,  Jong Chern Lee

IPC: G11C7/00

CPC classification number: G11C7/00

Abstract: A semiconductor apparatus having a plurality of chips stacked therein is disclosed. At least two of the plurality of chips are configured to receive a column command and generate a column control signal based on the column command. Generation timing of the column control signal generated based on a column command in one of the at least two of the plurality of chips substantially coincide with the generation timing in the other of the at least two of the plurality of chips.

Abstract translation: 公开了一种具有堆叠在其中的多个芯片的半导体装置。 多个芯片中的至少两个被配置为接收列命令，并且基于列命令生成列控制信号。 基于多个芯片中的至少两个芯片中的一个中的一个中的列命令产生的列控制信号的生成定时基本上与多个芯片中的至少两个芯片中的另一个中的另一个中的生成定时一致。

公开(公告)号：US20110103167A1

公开(公告)日：2011-05-05

申请号：US12839345

申请日：2010-07-19

Applicant: Kyeong Pil KANG ,  Jong Chern LEE

Inventor： Kyeong Pil KANG ,  Jong Chern LEE

IPC: G11C7/06

CPC classification number: G11C7/062 ,  G11C7/1069 ,  G11C7/1096

Abstract: A local sense amplifier of a semiconductor memory apparatus includes a read amplification unit configured to amplify data of first data lines and transfer the amplified data to second data lines during a read operation; and a write amplification unit configured to amplify data of the second data lines and transfer the amplified data to the first data lines during a write operation.

Abstract translation: 半导体存储装置的本地读出放大器包括：读取放大单元，被配置为在读取操作期间放大第一数据线的数据并将放大的数据传送到第二数据线; 以及写入放大单元，被配置为在写入操作期间放大第二数据线的数据并将放大的数据传送到第一数据线。

公开(公告)号：US20110001514A1

公开(公告)日：2011-01-06

申请号：US12624144

申请日：2009-11-23

Applicant: Hyun-Su Yoon ,  Jong-Chern Lee

Inventor： Hyun-Su Yoon ,  Jong-Chern Lee

IPC: H03K19/00

CPC classification number: H04L7/02 ,  H04L7/0045

Abstract: A command control circuit of a semiconductor integrated device includes a plurality of latches sequentially connected and receiving a command signal, and a plurality of selection switches configured to pass or to interrupt the command signal inputted to each one of the plurality of latches.

Abstract translation: 半导体集成装置的指令控制电路包括顺序地连接并接收命令信号的多个锁存器，以及被配置为通过或中断输入到多个锁存器中的每一个的指令信号的多个选择开关。

公开(公告)号：US20090231022A1

公开(公告)日：2009-09-17

申请号：US12327729

申请日：2008-12-03

Applicant: Jong Sam Kim ,  Jong Chern Lee

Inventor： Jong Sam Kim ,  Jong Chern Lee

IPC: G05F1/10

CPC classification number: G11C11/4085 ,  G11C5/145 ,  G11C11/4074 ,  H02M3/073 ,  H02M2003/077

Abstract: A pumping voltage generating circuit of a semiconductor memory apparatus, the pumping voltage generating circuit includes a detecting unit configured to compare a level of a pumping voltage with a level of a reference voltage to generate a detection signal, an oscillating signal generator configured to sequentially generate a first oscillating signal and a second oscillating signal in response to the detection signal, and to elevate frequencies of the first and second oscillating signals when the second oscillating signal is generated, a first pump configured to perform a pumping operation in response to the first oscillating signal, and a second pump configured to perform a pumping operation in response to the second oscillating signal, wherein output terminals of the first pump and the second pump are commonly connected, and the pumping voltage is output at the output terminals of the first pump and the second pump.

Abstract translation: 一种半导体存储装置的泵浦电压产生电路，所述泵送电压产生电路包括：检测单元，被配置为将泵浦电压的电平与参考电压的电平进行比较以产生检测信号;振荡信号发生器，被配置为顺序地产生 响应于所述检测信号的第一振荡信号和第二振荡信号，并且当产生所述第二振荡信号时提升所述第一和第二振荡信号的频率;第一泵，被配置为响应于所述第一振荡 信号，以及第二泵，被配置为响应于所述第二振荡信号执行泵送操作，其中所述第一泵和所述第二泵的输出端子共同连接，并且所述泵浦电压在所述第一泵的输出端子处输出， 第二个泵。

公开(公告)号：US07539064B2

公开(公告)日：2009-05-26

申请号：US11641857

申请日：2006-12-20

Applicant: Jong Chern Lee

Inventor： Jong Chern Lee

IPC: G11C11/34

CPC classification number: G11C7/1048 ,  G11C7/02

Abstract: A precharge circuit of a semiconductor memory apparatus includes a first precharge unit and a second precharge unit. The first precharge unit applies a first core voltage to a pair of local input/output lines, in response to a first precharge signal, to precharge the pair of local input/output lines. The second precharge unit applies a clamp voltage, which is generated using a first supply voltage, to the pair of local input/output lines, in response to the first precharge signal, to precharge the pair of local input/output lines.

Abstract translation: 半导体存储装置的预充电电路包括第一预充电单元和第二预充电单元。 第一预充电单元响应于第一预充电信号向一对本地输入/输出线施加第一芯电压，以对该对本地输入/输出线进行预充电。 第二预充电单元响应于第一预充电信号，向一对本地输入/输出线施加使用第一电源电压产生的钳位电压，以对该对本地输入/输出线进行预充电。

公开(公告)号：US20080136484A1

公开(公告)日：2008-06-12

申请号：US11826924

申请日：2007-07-19

Applicant: Dae-Suk Kim ,  Jong Chern Lee

Inventor： Dae-Suk Kim ,  Jong Chern Lee

IPC: H03H11/26

CPC classification number: G11C7/08

Abstract: A sense amplifier control signal generating circuit of a semiconductor memory apparatus is provided. The sense amplifier control signal generating circuit includes a timing control unit that models a transmission path of data from a memory cell to a sense amplifier through a bit line and generates a timing control signal at a sensing timing when the sense amplifier starts a sensing operation. A sense amplifier control signal generating unit receives the timing control signal and generates a sense amplifier control signal.

Abstract translation: 提供一种半导体存储装置的读出放大器控制信号发生电路。 读出放大器控制信号产生电路包括定时控制单元，其通过位线对来自存储单元的数据的传输路径进行建模，并在读出放大器开始感测操作时在感测定时产生定时控制信号。 读出放大器控制信号发生单元接收定时控制信号并产生读出放大器控制信号。