公开(公告)号：US20100117218A1

公开(公告)日：2010-05-13

申请号：US12458454

申请日：2009-07-13

申请人： Seung Wook Park ,  Young Do Kweon ,  Jin Gu Kim ,  Ju Pyo Hong ,  Hee Kon Lee ,  Hyung Jin Jeon ,  Jing Li Yuan ,  Jong Yun Lee

发明人： Seung Wook Park ,  Young Do Kweon ,  Jin Gu Kim ,  Ju Pyo Hong ,  Hee Kon Lee ,  Hyung Jin Jeon ,  Jing Li Yuan ,  Jong Yun Lee

IPC分类号： H01L23/498 ,  H01L21/56 ,  H01L21/60 ,  H01L23/29

CPC分类号： H01L23/3128 ,  H01L21/563 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5384 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/81 ,  H01L24/83 ,  H01L2224/05001 ,  H01L2224/05026 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05548 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/2402 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/81801 ,  H01L2224/83851 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/00011 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/15311 ,  H01L2924/351 ,  H01L2224/29075 ,  H01L2924/00014 ,  H01L2924/00

摘要： The present invention relates to a stacked wafer level package and a method of manufacturing the same. The stacked wafer level package in accordance with the present invention can improve a misalignment problem generated in a stacking process by performing a semiconductor chip mounting process, a rearrangement wiring layer forming process, the stacking process and so on after previously bonding internal connection means for interconnection between stacked electronic components to a conductive layer for forming a rearrangement wiring layer, thereby improving reliability and yield and reducing manufacturing cost.

摘要翻译： 本发明涉及层叠晶片级封装及其制造方法。 根据本发明的堆叠晶片级封装可以通过在预先接合用于互连的内部连接装置之后执行半导体芯片安装处理，重排布线层形成处理，堆叠处理等来改善堆叠处理中产生的未对准问题 在层叠的电子部件之间形成用于形成重排布线层的导电层，从而提高可靠性和产率，并降低制造成本。

公开(公告)号：US20100102426A1

公开(公告)日：2010-04-29

申请号：US12320286

申请日：2009-01-22

申请人： Seung Wook Park ,  Young Do Kweon ,  Jingli Yuan ,  Seon Hee Moon ,  Ju Pyo Hong ,  Jae Kwang Lee

发明人： Seung Wook Park ,  Young Do Kweon ,  Jingli Yuan ,  Seon Hee Moon ,  Ju Pyo Hong ,  Jae Kwang Lee

IPC分类号： H01L23/50 ,  H01L21/768

CPC分类号： H01L21/76898 ,  H01L21/481 ,  H01L23/3114 ,  H01L23/49827 ,  H01L2924/0002 ,  H01L2924/00

摘要： Disclosed herein is a dual face package and a method of manufacturing the same. The dual face package includes a semiconductor substrate including a through-electrode connected to a die pad disposed on one side of the semiconductor substrate, and a lower redistribution layer disposed on another side thereof and connected to the through-electrode, an insulating layer including a post electrode connected to the through-electrode, and an upper redistribution layer disposed on one side thereof and connected to the post electrode, and an adhesive layer disposed on the one side of the semiconductor substrate so as to attach the insulating layer to the semiconductor substrate such that the through-electrode is connected to the post electrode. The dual face package is produced by a simple process and is applicable to a large diameter wafer level package.

摘要翻译： 本文公开了双面包装及其制造方法。 双面包装包括半导体衬底，其包括连接到设置在半导体衬底的一侧的管芯焊盘的贯通电极以及设置在其另一侧并连接到通孔的下再分配层，绝缘层包括： 连接到所述贯通电极的后电极以及设置在其一侧并连接到所述柱电极的上再分配层，以及设置在所述半导体衬底的一侧上以将所述绝缘层附着到所述半导体衬底的粘合层 使得贯通电极连接到柱电极。 双面包装通过简单的工艺生产，适用于大直径晶圆级封装。

公开(公告)号：US20080290479A1

公开(公告)日：2008-11-27

申请号：US12153705

申请日：2008-05-22

申请人： Ju Pyo Hong ,  Seog Moon Choi ,  Tae Hoon Kim ,  Job Ha ,  Seung Wook Park

发明人： Ju Pyo Hong ,  Seog Moon Choi ,  Tae Hoon Kim ,  Job Ha ,  Seung Wook Park

IPC分类号： H01L23/495 ,  H01L21/60

CPC分类号： H01L21/50 ,  B81B2207/093 ,  B81C1/00301 ,  B81C2203/0118 ,  B81C2203/019 ,  H01L23/10 ,  H01L23/3114 ,  H01L2924/0002 ,  H01L2924/16195 ,  H01L2924/16235 ,  H03H9/1057 ,  H03H9/1071 ,  H01L2924/00

摘要： Provided are wafer level package with a sealing line that seals a device and includes electroconductive patterns as an electrical connection structure for the device, and a method of packaging the same. In the wafer level package, a device substrate includes a device region, where a device is mounted, on the top surface. A sealing line includes a plurality of non-electroconductive patterns and a plurality of electroconductive patterns, and seals the device region. A cap substrate includes a plurality of vias respectively connected to the electroconductive patterns and is attached to the device substrate by the sealing line. Therefore, a simplified wafer level package structure that accomplishes electric connection through electroconductive patterns of a sealing line can be formed without providing an electrode pad for electric connection with a device.

摘要翻译： 提供了具有密封设备并且包括作为设备的电连接结构的导电图案的密封线的晶片级封装以及其封装方法。 在晶片级封装中，器件衬底包括在顶表面上安装器件的器件区域。 密封线包括多个非导电图案和多个导电图案，并且密封该装置区域。 盖基板包括分别连接到导电图案的多个通孔，并通过密封线附接到器件基板。 因此，可以形成通过密封线的导电图案实现电连接的简化的晶片级封装结构，而不需要提供用于与器件电连接的电极焊盘。