公开(公告)号：US20080290479A1

公开(公告)日：2008-11-27

申请号：US12153705

申请日：2008-05-22

Applicant: Ju Pyo Hong ,  Seog Moon Choi ,  Tae Hoon Kim ,  Job Ha ,  Seung Wook Park

Inventor： Ju Pyo Hong ,  Seog Moon Choi ,  Tae Hoon Kim ,  Job Ha ,  Seung Wook Park

IPC: H01L23/495 ,  H01L21/60

CPC classification number: H01L21/50 ,  B81B2207/093 ,  B81C1/00301 ,  B81C2203/0118 ,  B81C2203/019 ,  H01L23/10 ,  H01L23/3114 ,  H01L2924/0002 ,  H01L2924/16195 ,  H01L2924/16235 ,  H03H9/1057 ,  H03H9/1071 ,  H01L2924/00

Abstract: Provided are wafer level package with a sealing line that seals a device and includes electroconductive patterns as an electrical connection structure for the device, and a method of packaging the same. In the wafer level package, a device substrate includes a device region, where a device is mounted, on the top surface. A sealing line includes a plurality of non-electroconductive patterns and a plurality of electroconductive patterns, and seals the device region. A cap substrate includes a plurality of vias respectively connected to the electroconductive patterns and is attached to the device substrate by the sealing line. Therefore, a simplified wafer level package structure that accomplishes electric connection through electroconductive patterns of a sealing line can be formed without providing an electrode pad for electric connection with a device.

Abstract translation: 提供了具有密封设备并且包括作为设备的电连接结构的导电图案的密封线的晶片级封装以及其封装方法。 在晶片级封装中，器件衬底包括在顶表面上安装器件的器件区域。 密封线包括多个非导电图案和多个导电图案，并且密封该装置区域。 盖基板包括分别连接到导电图案的多个通孔，并通过密封线附接到器件基板。 因此，可以形成通过密封线的导电图案实现电连接的简化的晶片级封装结构，而不需要提供用于与器件电连接的电极焊盘。

公开(公告)号：US20130147027A1

公开(公告)日：2013-06-13

申请号：US13403867

申请日：2012-02-23

Applicant: Job Ha

Inventor： Job Ha

IPC: H01L23/34

CPC classification number: H01L23/36 ,  H01L23/3735 ,  H01L23/49811 ,  H01L23/49833 ,  H01L25/0652 ,  H01L25/071 ,  H01L2224/06181 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/15192 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/00

Abstract: Disclosed herein is a semiconductor package.According to a preferred embodiment of the present invention, there is provided a semiconductor package, including: a first substrate having a first wiring pattern formed therein; a first semiconductor device mounted above the first substrate by being contacted with the first substrate; a second substrate having a second wiring pattern formed therein; a third semiconductor device mounted above the first semiconductor device and contacted with a lower portion of the second substrate; and a third substrate positioned between the first semiconductor device and the third semiconductor device and having a third wiring pattern including at least one upper electrode and lower electrode protruding outwardly, the lower electrode being contacted with the first semiconductor device and the upper electrode being contacted with the third semiconductor device.

Abstract translation: 这里公开了半导体封装。 根据本发明的优选实施例，提供一种半导体封装，包括：第一衬底，其中形成有第一布线图案; 通过与所述第一基板接触而安装在所述第一基板上方的第一半导体器件; 第二基板，其中形成有第二布线图案; 安装在所述第一半导体器件上方并与所述第二衬底的下部接触的第三半导体器件; 以及位于所述第一半导体器件和所述第三半导体器件之间并且具有包括至少一个向上突出的上电极和下电极的第三布线图案的第三衬底，所述下电极与所述第一半导体器件和所述上电极接触 第三半导体器件。

公开(公告)号：US20080283989A1

公开(公告)日：2008-11-20

申请号：US12153373

申请日：2008-05-16

Applicant: Won Kyu Jeung ,  Seog Moon Choi ,  Job Ha ,  Sang Hee Park ,  Tae Hoon Kim

Inventor： Won Kyu Jeung ,  Seog Moon Choi ,  Job Ha ,  Sang Hee Park ,  Tae Hoon Kim

IPC: H01L23/055 ,  H01L21/54

CPC classification number: H01L23/26 ,  H01L23/055 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Provided are a wafer level package and a wafer level packaging method, which are capable of performing an attaching process at a low temperature and preventing contamination of internal devices. In the wafer level package, a device substrate includes a device region, where a device is formed, and internal pads on the top surface. The internal pads are electrically connected to the device. A cap substrate includes a getter corresponding to the device on the bottom surface. A plurality of sealing/attaching members are provided between the device substrate and the cap substrate to attach the device substrate and the cap substrate and seal the device region and the getter. The sealing/attaching members are formed of polymer. A plurality of vias penetrate the cap substrate and are connected to the internal pads. The getter provided in the sealed space defined by the sealing/attaching members can prevent the devices of the device region from being contaminated by moisture or foreign particles generated during the fabrication process, and the sealing/attaching process can be performed at a lower temperature compared with a typical sealing/attaching process using a metal.

Abstract translation: 提供了能够在低温下执行附着处理并防止内部装置的污染的晶片级封装和晶片级封装方法。 在晶片级封装中，器件衬底包括其中形成器件的器件区域和顶表面上的内部焊盘。 内部焊盘电连接到设备。 盖基板包括对应于底表面上的装置的吸气剂。 在装置基板和盖基板之间设置多个密​​封/附接构件，以附接装置基板和盖基板，并密封装置区域和吸气剂。 密封/附接构件由聚合物形成。 多个通孔穿过盖基板并连接到内部焊盘。 设置在由密封/附接构件限定的密封空间中的吸气剂可以防止装置区域的装置被制造过程中产生的湿气或异物污染，并且密封/附着过程可以在较低的温度下进行比较 具有典型的使用金属的密封/附着工艺。

公开(公告)号：US20140001613A1

公开(公告)日：2014-01-02

申请号：US13603654

申请日：2012-09-05

Applicant: Job HA

Inventor： Job HA

IPC: H01L23/495

CPC classification number: H01L23/24 ,  H01L23/3107 ,  H01L23/3135 ,  H01L23/4334 ,  H01L23/49555 ,  H01L23/49575 ,  H01L23/49586 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/00

Abstract: There is provided semiconductor package including: an internal lead having at least one electronic component mounted on a surface thereof; a heat sink disposed below the internal lead; a molded portion sealing the at least one electronic component, the internal lead and the heat sink; an external lead extended from the internal lead and protruding outwardly from the molded portion in a radial direction; a heat radiating member attached to the heat sink and a surface of the molded portion; and an insulating coating film formed on a surface of the external lead.

Abstract translation: 提供的半导体封装包括：具有安装在其表面上的至少一个电子部件的内部引线; 设置在内部引线下方的散热器; 密封所述至少一个电子部件，所述内部引线和所述散热器的模制部分; 外部引线从内部引线延伸并在径向方向上从模制部分向外突出; 附接到所述散热器的散热构件和所述模制部分的表面; 以及形成在外部引线的表面上的绝缘涂膜。

公开(公告)号：US20130134569A1

公开(公告)日：2013-05-30

申请号：US13402117

申请日：2012-02-22

Applicant: Job Ha

Inventor： Job Ha

IPC: H01L23/495

CPC classification number: H01L23/053 ,  H01L23/24 ,  H01L23/49811 ,  H01L24/73 ,  H01L25/072 ,  H01L25/162 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/48137 ,  H01L2224/48139 ,  H01L2224/48227 ,  H01L2224/4846 ,  H01L2224/73265 ,  H01L2924/181 ,  H01L2924/19105 ,  H01L2924/00012 ,  H01L2924/0665

Abstract: Disclosed herein is a semiconductor package.The semiconductor package includes: a substrate having a semiconductor device mounted on a top portion thereof; a housing surrounding the semiconductor device and the substrate so as to isolate them from the outside; at least one lead frame disposed on the top portion of the substrate while being spaced apart from one another; and a clip electrically connecting the substrate with at least one lead frame.

Abstract translation: 这里公开了半导体封装。 半导体封装包括：具有安装在其顶部上的半导体器件的衬底; 围绕半导体器件和衬底的壳体，以将它们与外部隔离; 至少一个引线框架设置在所述基板的顶部上，同时彼此间隔开; 以及将所述基板与至少一个引线框架电连接的夹子。

公开(公告)号：US07911043B2

公开(公告)日：2011-03-22

申请号：US12153705

申请日：2008-05-22

Applicant: Ju Pyo Hong ,  Seog Moon Choi ,  Tae Hoon Kim ,  Job Ha ,  Seung Wook Park

Inventor： Ju Pyo Hong ,  Seog Moon Choi ,  Tae Hoon Kim ,  Job Ha ,  Seung Wook Park

IPC: H01L23/02

CPC classification number: H01L21/50 ,  B81B2207/093 ,  B81C1/00301 ,  B81C2203/0118 ,  B81C2203/019 ,  H01L23/10 ,  H01L23/3114 ,  H01L2924/0002 ,  H01L2924/16195 ,  H01L2924/16235 ,  H03H9/1057 ,  H03H9/1071 ,  H01L2924/00

Abstract: Provided are wafer level package with a sealing line that seals a device and includes electroconductive patterns as an electrical connection structure for the device, and a method of packaging the same. In the wafer level package, a device substrate includes a device region, where a device is mounted, on the top surface. A sealing line includes a plurality of non-electroconductive patterns and a plurality of electroconductive patterns, and seals the device region. A cap substrate includes a plurality of vias respectively connected to the electroconductive patterns and is attached to the device substrate by the sealing line. Therefore, a simplified wafer level package structure that accomplishes electric connection through electroconductive patterns of a sealing line can be formed without providing an electrode pad for electric connection with a device.

Abstract translation: 提供了具有密封设备并且包括作为设备的电连接结构的导电图案的密封线的晶片级封装以及其封装方法。 在晶片级封装中，器件衬底包括在顶表面上安装器件的器件区域。 密封线包括多个非导电图案和多个导电图案，并且密封该装置区域。 盖基板包括分别连接到导电图案的多个通孔，并通过密封线附接到器件基板。 因此，可以形成通过密封线的导电图案实现电连接的简化的晶片级封装结构，而不需要提供用于与器件电连接的电极焊盘。

公开(公告)号：US20130285232A1

公开(公告)日：2013-10-31

申请号：US13546433

申请日：2012-07-11

Applicant: Job Ha

Inventor： Job Ha

IPC: H01L23/48

CPC classification number: H05K3/325 ,  H01L25/16 ,  H01L2924/0002 ,  H01L2924/15312 ,  H01L2924/15322 ,  H05K3/326 ,  H05K2201/068 ,  H05K2201/10378 ,  H05K2201/1059 ,  H05K2201/10598 ,  H05K2201/2036 ,  H01L2924/00

Abstract: Disclosed herein is a semiconductor package module, including: a circuit board having connection pads formed on one surface thereof; a semiconductor package including lead terminals protruded out of a housing; and an interposer positioned between the circuit board and the semiconductor package, the interposer including a body allowing the circuit board and the semiconductor package to be spaced apart from each other and elastic members contacted with the connection pads and the lead terminals.

Abstract translation: 这里公开了一种半导体封装模块，包括：具有形成在其一个表面上的连接焊盘的电路板; 半导体封装，其包括从壳体突出的引线端子; 以及位于所述电路板和所述半导体封装之间的插入器，所述插入器包括允许所述电路板和所述半导体封装彼此间隔开的主体以及与所述连接焊盘和所述引线端子接触的弹性构件。