公开(公告)号：US08704350B2

公开(公告)日：2014-04-22

申请号：US12458454

申请日：2009-07-13

申请人： Seung Wook Park ,  Young Do Kweon ,  Jin Gu Kim ,  Ju Pyo Hong ,  Hee Kon Lee ,  Hyung Jin Jeon ,  Jing Li Yuan ,  Jong Yun Lee

发明人： Seung Wook Park ,  Young Do Kweon ,  Jin Gu Kim ,  Ju Pyo Hong ,  Hee Kon Lee ,  Hyung Jin Jeon ,  Jing Li Yuan ,  Jong Yun Lee

IPC分类号： H01L23/02 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L23/3128 ,  H01L21/563 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5384 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/81 ,  H01L24/83 ,  H01L2224/05001 ,  H01L2224/05026 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05548 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/2402 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/81801 ,  H01L2224/83851 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/00011 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/15311 ,  H01L2924/351 ,  H01L2224/29075 ,  H01L2924/00014 ,  H01L2924/00

摘要： The present invention relates to a stacked wafer level package and a method of manufacturing the same. The stacked wafer level package in accordance with the present invention can improve a misalignment problem generated in a stacking process by performing a semiconductor chip mounting process, a rearrangement wiring layer forming process, the stacking process and so on after previously bonding internal connection means for interconnection between stacked electronic components to a conductive layer for forming a rearrangement wiring layer, thereby improving reliability and yield and reducing manufacturing cost.

摘要翻译： 本发明涉及层叠晶片级封装及其制造方法。 根据本发明的堆叠晶片级封装可以通过在预先接合用于互连的内部连接装置之后执行半导体芯片安装处理，重排布线层形成处理，堆叠处理等来改善堆叠处理中产生的未对准问题 在层叠的电子部件之间形成用于形成重排布线层的导电层，从而提高可靠性和产率，并降低制造成本。

公开(公告)号：US20100117218A1

公开(公告)日：2010-05-13

申请号：US12458454

申请日：2009-07-13

申请人： Seung Wook Park ,  Young Do Kweon ,  Jin Gu Kim ,  Ju Pyo Hong ,  Hee Kon Lee ,  Hyung Jin Jeon ,  Jing Li Yuan ,  Jong Yun Lee

发明人： Seung Wook Park ,  Young Do Kweon ,  Jin Gu Kim ,  Ju Pyo Hong ,  Hee Kon Lee ,  Hyung Jin Jeon ,  Jing Li Yuan ,  Jong Yun Lee

IPC分类号： H01L23/498 ,  H01L21/56 ,  H01L21/60 ,  H01L23/29

CPC分类号： H01L23/3128 ,  H01L21/563 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5384 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/81 ,  H01L24/83 ,  H01L2224/05001 ,  H01L2224/05026 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05548 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/2402 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/81801 ,  H01L2224/83851 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/00011 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/15311 ,  H01L2924/351 ,  H01L2224/29075 ,  H01L2924/00014 ,  H01L2924/00

摘要： The present invention relates to a stacked wafer level package and a method of manufacturing the same. The stacked wafer level package in accordance with the present invention can improve a misalignment problem generated in a stacking process by performing a semiconductor chip mounting process, a rearrangement wiring layer forming process, the stacking process and so on after previously bonding internal connection means for interconnection between stacked electronic components to a conductive layer for forming a rearrangement wiring layer, thereby improving reliability and yield and reducing manufacturing cost.

摘要翻译： 本发明涉及层叠晶片级封装及其制造方法。 根据本发明的堆叠晶片级封装可以通过在预先接合用于互连的内部连接装置之后执行半导体芯片安装处理，重排布线层形成处理，堆叠处理等来改善堆叠处理中产生的未对准问题 在层叠的电子部件之间形成用于形成重排布线层的导电层，从而提高可靠性和产率，并降低制造成本。

公开(公告)号：US08658467B2

公开(公告)日：2014-02-25

申请号：US12929703

申请日：2011-02-09

申请人： Seung Wook Park ,  Young Do Kweon ,  Jin Gu Kim ,  Ju Pyo Hong ,  Hee Kon Lee ,  Hyung Jin Jeon ,  Yuan Jing Li ,  Jong Yun Lee

发明人： Seung Wook Park ,  Young Do Kweon ,  Jin Gu Kim ,  Ju Pyo Hong ,  Hee Kon Lee ,  Hyung Jin Jeon ,  Yuan Jing Li ,  Jong Yun Lee

IPC分类号： H01L21/00

CPC分类号： H01L23/3128 ,  H01L21/563 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5384 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/81 ,  H01L24/83 ,  H01L2224/05001 ,  H01L2224/05026 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05548 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/2402 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/81801 ,  H01L2224/83851 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/00011 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/15311 ,  H01L2924/351 ,  H01L2224/29075 ,  H01L2924/00014 ,  H01L2924/00

摘要： A method of manufacturing a stacked wafer level package includes: preparing a substrate; forming a conductive layer on the substrate; forming chip connection pads and internal connection pads on the conductive layer; forming solder balls connected to the internal connection pads; mounting a semiconductor chip on the conductive layer to be connected to the chip connection pads; forming a sealing member to seal the solder balls and the semiconductor chip; separating the substrate from the conductive layer; forming a rearrangement wiring layer by etching the conductive layer; forming an external connection on the rearrangement wiring layer; forming contact holes in the sealing member to expose the solder balls; and stacking an electronic component to be electrically connected to the solder balls exposed through the contact holes.

摘要翻译： 层叠晶片级封装的制造方法包括：准备基板; 在所述基板上形成导电层; 在导电层上形成芯片连接焊盘和内部连接焊盘; 形成连接到内部连接焊盘的焊球; 将半导体芯片安装在所述导电层上以连接到所述芯片连接焊盘; 形成密封构件以密封焊球和半导体芯片; 将衬底与导电层分离; 通过蚀刻导电层形成重排布线层; 在所述重排布线层上形成外部连接; 在所述密封构件中形成接触孔以暴露所述焊球; 并且堆叠要电连接到通过接触孔暴露的焊料球的电子部件。

公开(公告)号：US20110129960A1

公开(公告)日：2011-06-02

申请号：US12929703

申请日：2011-02-09

申请人： Seung Wook Park ,  Young Do Kweon ,  Jin Gu Kim ,  Ju Pyo Hong ,  Hee Kon Lee ,  Hyung Jin Jeon ,  Yuan Jing Li ,  Jong Yun Lee

发明人： Seung Wook Park ,  Young Do Kweon ,  Jin Gu Kim ,  Ju Pyo Hong ,  Hee Kon Lee ,  Hyung Jin Jeon ,  Yuan Jing Li ,  Jong Yun Lee

IPC分类号： H01L21/50

CPC分类号： H01L23/3128 ,  H01L21/563 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5384 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/81 ,  H01L24/83 ,  H01L2224/05001 ,  H01L2224/05026 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05548 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/2402 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/81801 ,  H01L2224/83851 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/00011 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/15311 ,  H01L2924/351 ,  H01L2224/29075 ,  H01L2924/00014 ,  H01L2924/00

摘要： A method of manufacturing a stacked wafer level package includes: preparing a substrate; forming a conductive layer on the substrate; forming chip connection pads and internal connection pads on the conductive layer; forming solder balls connected to the internal connection pads; mounting a semiconductor chip on the conductive layer to be connected to the chip connection pads; forming a sealing member to seal the solder balls and the semiconductor chip; separating the substrate from the conductive layer; forming a rearrangement wiring layer by etching the conductive layer; forming an external connection on the rearrangement wiring layer; forming contact holes in the sealing member to expose the solder balls; and stacking an electronic component to be electrically connected to the solder balls exposed through the contact holes.

摘要翻译： 层叠晶片级封装的制造方法包括：准备基板; 在所述基板上形成导电层; 在导电层上形成芯片连接焊盘和内部连接焊盘; 形成连接到内部连接焊盘的焊球; 将半导体芯片安装在所述导电层上以连接到所述芯片连接焊盘; 形成密封构件以密封焊球和半导体芯片; 将衬底与导电层分离; 通过蚀刻导电层形成重排布线层; 在所述重排布线层上形成外部连接; 在所述密封构件中形成接触孔以暴露所述焊球; 并且堆叠要电连接到通过接触孔暴露的焊料球的电子部件。

公开(公告)号：US20100159646A1

公开(公告)日：2010-06-24

申请号：US12453273

申请日：2009-05-05

申请人： Jin Gu Kim ,  Young Do Kweon ,  Hyung Jin Jeon ,  Seung Wook Park ,  Hee Kon Lee ,  Seon Hee Moon

发明人： Jin Gu Kim ,  Young Do Kweon ,  Hyung Jin Jeon ,  Seung Wook Park ,  Hee Kon Lee ,  Seon Hee Moon

IPC分类号： H01L21/78

CPC分类号： H01L21/561 ,  H01L23/24 ,  H01L23/3121 ,  H01L24/94 ,  H01L2924/09701 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/00

摘要： The present invention relates to a method of manufacturing a wafer level package including the steps of: preparing a substrate wafer including a plurality of pads formed on a bottom surface, a plurality of chips positioned on a top surface, and dicing lines for dividing the chips; forming external connection units on the pads; coating resin on the dicing lines by positioning masks on the substrate wafer to expose only the dicing lines; removing the masks; encapsulating the chips positioned between the resin by coating the chips with encapsulant; removing the resin coated on the dicing lines; and cutting a wafer level package along the dicing lines exposed by removing the resin into units.

摘要翻译： 本发明涉及一种制造晶片级封装的方法，包括以下步骤：制备包括形成在底表面上的多个焊盘，位于顶表面上的多个芯片的基板晶片和用于分割芯片的切割线 ; 在焊盘上形成外部连接单元; 通过将衬底定位在衬底晶片上以仅露出切割线，在切割线上涂覆树脂; 去除面具; 通过用密封剂涂覆芯片来封装位于树脂之间的芯片; 去除涂覆在切割线上的树脂; 以及沿着通过将树脂去除单元暴露的切割线切割晶片级封装。

公开(公告)号：US20110201156A1

公开(公告)日：2011-08-18

申请号：US13064878

申请日：2011-04-22

申请人： Jin Gu Kim ,  Young Do Kweon ,  Hyung Jin Jeon ,  Seung Wook Park ,  Hee Kon Lee ,  Seon Hee Moon

发明人： Jin Gu Kim ,  Young Do Kweon ,  Hyung Jin Jeon ,  Seung Wook Park ,  Hee Kon Lee ,  Seon Hee Moon

IPC分类号： H01L21/50

CPC分类号： H01L21/561 ,  H01L23/24 ,  H01L23/3121 ,  H01L24/94 ,  H01L2924/09701 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/00

摘要： A method of manufacturing a wafer level package including: preparing a substrate wafer including a plurality of pads formed on a bottom surface, a plurality of chips positioned on a top surface, and dicing lines for dividing the chips; forming external connection units on the pads; coating resin on the dicing lines by positioning masks on the substrate wafer to expose only the dicing lines; removing the masks; encapsulating the chips positioned between the resin by coating the chips with encapsulant and cutting a wafer level package along the dicing lines coated with the resin into units.

摘要翻译： 一种制造晶片级封装的方法，包括：准备包括形成在底表面上的多个焊盘，位于顶表面上的多个芯片的基板晶片和用于分割芯片的切割线; 在焊盘上形成外部连接单元; 通过将衬底定位在衬底晶片上以仅露出切割线，在切割线上涂覆树脂; 去除面具; 通过用密封剂涂覆芯片来封装位于树脂之间的芯片，并沿着涂覆有树脂的切割线将晶片级封装切割成单元。

公开(公告)号：US07947530B2

公开(公告)日：2011-05-24

申请号：US12453273

申请日：2009-05-05

申请人： Jin Gu Kim ,  Young Do Kweon ,  Hyung Jin Jeon ,  Seung Wook Park ,  Hee Kon Lee ,  Seon Hee Moon

发明人： Jin Gu Kim ,  Young Do Kweon ,  Hyung Jin Jeon ,  Seung Wook Park ,  Hee Kon Lee ,  Seon Hee Moon

IPC分类号： H01L21/44 ,  H01L21/48 ,  H01L21/50

CPC分类号： H01L21/561 ,  H01L23/24 ,  H01L23/3121 ,  H01L24/94 ,  H01L2924/09701 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/00

摘要： The present invention relates to a method of manufacturing a wafer level package including the steps of: preparing a substrate wafer including a plurality of pads formed on a bottom surface, a plurality of chips positioned on a top surface, and dicing lines for dividing the chips; forming external connection units on the pads; coating resin on the dicing lines by positioning masks on the substrate wafer to expose only the dicing lines; removing the masks; encapsulating the chips positioned between the resin by coating the chips with encapsulant; removing the resin coated on the dicing lines; and cutting a wafer level package along the dicing lines exposed by removing the resin into units.

摘要翻译： 本发明涉及一种制造晶片级封装的方法，包括以下步骤：制备包括形成在底表面上的多个焊盘，位于顶表面上的多个芯片的基板晶片和用于分割芯片的切割线 ; 在焊盘上形成外部连接单元; 通过将衬底定位在衬底晶片上以仅露出切割线，在切割线上涂覆树脂; 去除面具; 通过用密封剂涂覆芯片来封装位于树脂之间的芯片; 去除涂覆在切割线上的树脂; 以及沿着通过将树脂去除单元暴露的切割线切割晶片级封装。

公开(公告)号：US20100149770A1

公开(公告)日：2010-06-17

申请号：US12453272

申请日：2009-05-05

申请人： Seung Wook Park ,  Jin Gu Kim ,  Jong Hwan Baek ,  Jong Yun Lee ,  Hyung Jin Jeon ,  Young Do Kweon

发明人： Seung Wook Park ,  Jin Gu Kim ,  Jong Hwan Baek ,  Jong Yun Lee ,  Hyung Jin Jeon ,  Young Do Kweon

IPC分类号： H01L23/538

CPC分类号： H01L25/0652 ,  H01L2224/16145 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/73207 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00

摘要： The present invention relates to a semiconductor stack package including: a printed circuit board; a first semiconductor chip mounted on the printed circuit board; a second semiconductor chip mounted on the printed circuit board in parallel with the first semiconductor chip; a first rearrangement wiring layer positioned on the first semiconductor chip; a second rearrangement wiring layer which constitutes one circuit together with the first rearrangement wiring layer and is positioned on the second semiconductor chip; and a third semiconductor chip which is electrically connected to the first and second rearrangement wiring layers and of which both ends are separately positioned on the first and second semiconductor chips.

摘要翻译： 本发明涉及一种半导体堆叠封装，包括：印刷电路板; 安装在印刷电路板上的第一半导体芯片; 与所述第一半导体芯片并联安装在所述印刷电路板上的第二半导体芯片; 位于第一半导体芯片上的第一重排布线层; 第二重排布线层，与第一重排布线层一起构成一个电路，并且位于第二半导体芯片上; 以及第三半导体芯片，其电连接到第一和第二重排布线层，并且其两端分别位于第一和第二半导体芯片上。

公开(公告)号：US08143099B2

公开(公告)日：2012-03-27

申请号：US12453274

申请日：2009-05-05

申请人： Seung Wook Park ,  Jin Gu Kim ,  Jong Hwan Baek ,  Jong Yun Lee ,  Hyung Jin Jeon ,  Young Do Kweon

发明人： Seung Wook Park ,  Jin Gu Kim ,  Jong Hwan Baek ,  Jong Yun Lee ,  Hyung Jin Jeon ,  Young Do Kweon

IPC分类号： H01L21/00

CPC分类号： H01L21/4832 ,  H01L21/563 ,  H01L21/568 ,  H01L23/3107 ,  H01L23/5389 ,  H01L2224/12105 ,  H01L2224/73204 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/09701 ,  H01L2924/15311 ,  H01L2224/0401

摘要： The present invention relates to a method of manufacturing a semiconductor package capable of simplifying a process and remarkably reducing a production cost by including the steps of: preparing a different bonded panel including at least one metal layer; forming a pad unit electrically connected to the metal layer; mounting a semiconductor chip over the different bonded panel to be electrically connected to the pad unit; sealing the semiconductor chip; forming a rearrangement wiring layer by etching the metal layer; and forming an external connection unit electrically connected to the rearrangement wiring layer.

摘要翻译： 本发明涉及一种制造半导体封装的方法，其能够简化工艺并显着降低生产成本，包括以下步骤：制备包括至少一个金属层的不同键合板; 形成电连接到所述金属层的焊盘单元; 将半导体芯片安装在所述不同的接合面板上以电连接到所述焊盘单元; 密封半导体芯片; 通过蚀刻金属层形成重排布线层; 以及形成与所述重排布线层电连接的外部连接单元。

公开(公告)号：US20100144152A1

公开(公告)日：2010-06-10

申请号：US12453274

申请日：2009-05-05

申请人： Seung Wook Park ,  Jin Gu Kim ,  Jong Hwan Baek ,  Jong Yun Lee ,  Hyung Jin Jeon ,  Young Do Kweon

发明人： Seung Wook Park ,  Jin Gu Kim ,  Jong Hwan Baek ,  Jong Yun Lee ,  Hyung Jin Jeon ,  Young Do Kweon

IPC分类号： H01L21/302

CPC分类号： H01L21/4832 ,  H01L21/563 ,  H01L21/568 ,  H01L23/3107 ,  H01L23/5389 ,  H01L2224/12105 ,  H01L2224/73204 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/09701 ,  H01L2924/15311 ,  H01L2224/0401

摘要： The present invention relates to a method of manufacturing a semiconductor package capable of simplifying a process and remarkably reducing a production cost by including the steps of: preparing a different bonded panel including at least one metal layer; forming a pad unit electrically connected to the metal layer; mounting a semiconductor chip over the different bonded panel to be electrically connected to the pad unit; sealing the semiconductor chip; forming a rearrangement wiring layer by etching the metal layer; and forming an external connection unit electrically connected to the rearrangement wiring layer.

摘要翻译： 本发明涉及一种制造半导体封装的方法，其能够简化工艺并显着降低生产成本，包括以下步骤：制备包括至少一个金属层的不同键合板; 形成电连接到所述金属层的焊盘单元; 将半导体芯片安装在所述不同的接合面板上以电连接到所述焊盘单元; 密封半导体芯片; 通过蚀刻金属层形成重排布线层; 以及形成与所述重排布线层电连接的外部连接单元。