公开(公告)号：US07221014B2

公开(公告)日：2007-05-22

申请号：US11015993

申请日：2004-12-17

Applicant: Doo-hoon Goo ,  Jung-hyeon Lee ,  Gi-sung Yeo ,  Han-ku Cho ,  Sang-gyun Woo

Inventor： Doo-hoon Goo ,  Jung-hyeon Lee ,  Gi-sung Yeo ,  Han-ku Cho ,  Sang-gyun Woo

IPC: H01L29/74 ,  H01L29/76

CPC classification number: H01L27/10888 ,  H01L27/0207 ,  H01L27/10814

Abstract: DRAM devices include a plurality of word lines extending in a first direction and a plurality of bit lines extending in a second direction and intersecting the word lines. A plurality of active regions is provided that are electrically coupled to the word lines and the bit lines. Each of the active regions defines a single unit memory cell having an area of 6F2 in terms of a minimum line width F. Each of the active regions may be overlapped by only one word line and the active regions may be defined by an isolation region.

Abstract translation: DRAM装置包括沿第一方向延伸的多个字线和沿第二方向延伸并与字线相交的多个位线。 提供了多个有源区域，其被电耦合到字线和位线。 每个有源区域以最小线宽度F来限定具有6F 2的面积的单个单元存储单元。每个有源区域可以仅由一条字线重叠，并且有源区域 可以由隔离区限定。

公开(公告)号：US20070108491A1

公开(公告)日：2007-05-17

申请号：US11621617

申请日：2007-01-10

Applicant: Jung-Hyeon Lee ,  Gi-Sung Yeo ,  Doo-Hoon Goo ,  Woo-Sung Han

Inventor： Jung-Hyeon Lee ,  Gi-Sung Yeo ,  Doo-Hoon Goo ,  Woo-Sung Han

IPC: H01L29/94

CPC classification number: H01L27/10885 ,  H01L27/0207 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/10888 ,  H01L27/10891

Abstract: A semiconductor memory device includes a plurality of rows, each row comprising a plurality of active regions arranged at a pitch wherein the active regions in adjacent rows are shifted with respect to each other by one half of the pitch, wherein a distance between each active region in a row is equal to a distance between active regions in adjacent rows.

Abstract translation: 半导体存储器件包括多行，每行包括以间距排列的多个有源区，其中相邻行中的有源区相对于间距彼此偏移一半，其中每个有源区之间的距离 在一行中等于相邻行中的活动区域之间的距离。

公开(公告)号：US07064051B2

公开(公告)日：2006-06-20

申请号：US10944151

申请日：2004-09-16

Applicant: Eun-Mi Lee ,  Doo-Hoon Goo ,  Jung-Hyeon Lee ,  Gi-Sung Yeo

Inventor： Eun-Mi Lee ,  Doo-Hoon Goo ,  Jung-Hyeon Lee ,  Gi-Sung Yeo

IPC: H01L21/3205 ,  H01L21/4763

CPC classification number: H01L21/76897 ,  H01L23/485 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Embodiments of the invention provide methods of forming SAC pads in non-straight semiconductor device having non-straight type or separate type active regions. A plurality of gate line structures extending in one direction may be formed on a semiconductor substrate having non-straight active regions. An interlayer insulating layer covering gate line structures may be formed on the gate line structures. Then, a photo-resist layer may be formed on the interlayer insulating layer. A photo-resist pattern may be formed through exposing and developing the photo-resist layer by using a photo-mask having, for example, a bar type, a wave type, or a reverse active type pattern. Then, contact holes exposing source/drain regions may be formed by etching the interlayer insulating layer using the photo-resist pattern as an etching mask. Contact pads may then be formed by filling the contact holes with a conductive material.

Abstract translation: 本发明的实施例提供了在具有非直型或分离型有源区的非直线半导体器件中形成SAC焊盘的方法。 可以在具有非直线活性区域的半导体衬底上形成沿一个方向延伸的多个栅极线结构。 覆盖栅极线结构的层间绝缘层可以形成在栅极线结构上。 然后，可以在层间绝缘层上形成光致抗蚀剂层。 可以通过使用具有例如条形，波型或反向活性型图案的光掩模，通过曝光和显影光致抗蚀剂层来形成光刻胶图案。 然后，可以通过使用光刻胶图案作为蚀刻掩模蚀刻层间绝缘层来形成暴露源极/漏极区的接触孔。 然后可以通过用导电材料填充接触孔来形成接触垫。

公开(公告)号：US20050167758A1

公开(公告)日：2005-08-04

申请号：US11054593

申请日：2005-02-09

Applicant: Tae-hyuk Ahn ,  Myeong-cheol Kim ,  Jung-hyeon Lee ,  Byeong-yun Nam ,  Gyung-jin Min

Inventor： Tae-hyuk Ahn ,  Myeong-cheol Kim ,  Jung-hyeon Lee ,  Byeong-yun Nam ,  Gyung-jin Min

IPC: H01L27/10 ,  H01L21/60 ,  H01L21/8242 ,  H01L27/108 ,  H01L31/113

CPC classification number: H01L27/10855 ,  H01L21/76897 ,  H01L27/10814 ,  H01L27/10888

Abstract: A semiconductor memory device having self-aligned contacts, capable of preventing a short-circuit between contacts for bit lines and contacts for storage electrodes and improving a process margin, and a method of fabricating the same are provided. The semiconductor memory device having self-aligned contacts includes a plurality of gate electrode patterns arranged in parallel on a semiconductor substrate, in which a plurality of first spacers are formed along the sidewalls of the gate electrode patterns, a first interdielectric layer formed on the entire surface of a resultant in which the first spacers are formed, a plurality of bit line patterns arranged in parallel on the first interdielectric layer to be perpendicular to the gate electrode patterns, in which a plurality of second spacers are formed along the sidewalls of the bit line patterns, a plurality of contacts for bit lines self-aligned with the first spacers, a second interdielectric layer formed on the entire surface of a resultant in which the second spacers are formed, and a plurality of contacts for storage electrodes simultaneously self-aligned with the second and first spacers.

公开(公告)号：US20050164100A1

公开(公告)日：2005-07-28

申请号：US11084327

申请日：2005-03-18

Applicant: In-sung Kim ,  Jung-hyeon Lee ,  Sung-gon Jung

Inventor： In-sung Kim ,  Jung-hyeon Lee ,  Sung-gon Jung

IPC: G03F1/00 ,  G03F1/29 ,  G03F1/32 ,  G03F1/36 ,  G03F1/54 ,  G03F1/68 ,  G03F1/70 ,  H01L21/027 ,  G03F9/00 ,  G03C5/00

CPC classification number: G03F1/32 ,  G03F1/36

Abstract: A phase shifting mask (PSM) for manufacturing a semiconductor device and a method of fabricating the same includes a transparent substrate, a main pattern formed on the transparent substrate and comprising a first phase shifting layer having a first optical transmittance greater than 0, and at least one assistant pattern formed on the transparent substrate proximal to the main pattern for phase-shifting by the same degree as the main pattern and having a second optical transmittance, which is less than the first optical transmittance.

Abstract translation: 用于制造半导体器件的相移掩模（PSM）及其制造方法包括：透明基板，形成在透明基板上的主图案，其包括第一透光率大于0的第一相移层，以及第 至少一个辅助图案形成在靠近主图案的透明基板上，用于与主图案相同程度的相移，并具有小于第一光透射率的第二光透射率。