公开(公告)号：US06885052B2

公开(公告)日：2005-04-26

申请号：US09790240

申请日：2001-02-21

申请人： Tae-hyuk Ahn ,  Myeong-cheol Kim ,  Jung-hyeon Lee ,  Byeong-yun Nam ,  Gyung-jin Min

发明人： Tae-hyuk Ahn ,  Myeong-cheol Kim ,  Jung-hyeon Lee ,  Byeong-yun Nam ,  Gyung-jin Min

IPC分类号： H01L27/10 ,  H01L21/60 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

CPC分类号： H01L27/10855 ,  H01L21/76897 ,  H01L27/10814 ,  H01L27/10888

摘要： A semiconductor memory device having self-aligned contacts, capable of preventing a short-circuit between contacts for bit lines and contacts for storage electrodes and improving a process margin, and a method of fabricating the same are provided. The semiconductor memory device having self-aligned contacts includes a plurality of gate electrode patterns arranged in parallel on a semiconductor substrate, in which a plurality of first spacers are formed along the sidewalls of the gate electrode patterns, a first interdielectric layer formed on the entire surface of a resultant in which the first spacers are formed, a plurality of bit line patterns arranged in parallel on the first interdielectric layer to be perpendicular to the gate electrode patterns, in which a plurality of second spacers are formed along the sidewalls of the bit line patterns, a plurality of contacts for bit lines self-aligned with the first spacers, a second interdielectric layer formed on the entire surface of a resultant in which the second spacers are formed, and a plurality of contacts for storage electrodes simultaneously self-aligned with the second and first spacers.

摘要翻译： 一种具有自对准触点的半导体存储器件及其制造方法，其特征在于能够防止位线触点和存储电极触点之间的短路，并提高加工余量。 具有自对准触点的半导体存储器件包括平行布置在半导体衬底上的多个栅电极图案，其中多个第一间隔物沿着栅电极图案的侧壁形成，第一绝缘层整体形成 其中形成有第一间隔物的结果的表面，在第一电介质层上平行布置成垂直于栅极电极图案的多个位线图案，其中沿着该位的侧壁形成多个第二间隔物 线图案，用于与第一间隔物自对准的位线的多个触点，形成在其中形成有第二间隔物的结果的整个表面上的第二电介质层和用于存储电极的多个触点同时自对准 与第二和第一间隔物。

公开(公告)号：US07132708B2

公开(公告)日：2006-11-07

申请号：US11054593

申请日：2005-02-09

申请人： Tae-hyuk Ahn ,  Myeong-cheol Kim ,  Jung-hyeon Lee ,  Byeong-yun Nam ,  Gyung-jin Min

发明人： Tae-hyuk Ahn ,  Myeong-cheol Kim ,  Jung-hyeon Lee ,  Byeong-yun Nam ,  Gyung-jin Min

IPC分类号： H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

CPC分类号： H01L27/10855 ,  H01L21/76897 ,  H01L27/10814 ,  H01L27/10888

摘要： A semiconductor memory device having self-aligned contacts, capable of preventing a short-circuit between contacts for bit lines and contacts for storage electrodes and improving a process margin, and a method of fabricating the same are provided. The semiconductor memory device having self-aligned contacts includes a plurality of gate electrode patterns arranged in parallel on a semiconductor substrate, in which a plurality of first spacers are formed along the sidewalls of the gate electrode patterns, a first interdielectric layer formed on the entire surface of a resultant in which the first spacers are formed, a plurality of bit line patterns arranged in parallel on the first interdielectric layer to be perpendicular to the gate electrode patterns, in which a plurality of second spacers are formed along the sidewalls of the bit line patterns, a plurality of contacts for bit lines self-aligned with the first spacers, a second interdielectric layer formed on the entire surface of a resultant in which the second spacers are formed, and a plurality of contacts for storage electrodes simultaneously self-aligned with the second and first spacers.

摘要翻译： 一种具有自对准触点的半导体存储器件及其制造方法，其特征在于能够防止位线触点和存储电极触点之间的短路，并提高加工余量。 具有自对准触点的半导体存储器件包括平行布置在半导体衬底上的多个栅电极图案，其中多个第一间隔物沿着栅电极图案的侧壁形成，第一绝缘层整体形成 其中形成有第一间隔物的结果的表面，在第一电介质层上平行布置成垂直于栅极电极图案的多个位线图案，其中沿着该位的侧壁形成多个第二间隔物 线图案，用于与第一间隔物自对准的位线的多个触点，形成在其中形成有第二间隔物的结果的整个表面上的第二电介质层和用于存储电极的多个触点同时自对准 与第二和第一间隔物。

公开(公告)号：US20050167758A1

公开(公告)日：2005-08-04

申请号：US11054593

申请日：2005-02-09

申请人： Tae-hyuk Ahn ,  Myeong-cheol Kim ,  Jung-hyeon Lee ,  Byeong-yun Nam ,  Gyung-jin Min

发明人： Tae-hyuk Ahn ,  Myeong-cheol Kim ,  Jung-hyeon Lee ,  Byeong-yun Nam ,  Gyung-jin Min

IPC分类号： H01L27/10 ,  H01L21/60 ,  H01L21/8242 ,  H01L27/108 ,  H01L31/113

CPC分类号： H01L27/10855 ,  H01L21/76897 ,  H01L27/10814 ,  H01L27/10888

摘要： A semiconductor memory device having self-aligned contacts, capable of preventing a short-circuit between contacts for bit lines and contacts for storage electrodes and improving a process margin, and a method of fabricating the same are provided. The semiconductor memory device having self-aligned contacts includes a plurality of gate electrode patterns arranged in parallel on a semiconductor substrate, in which a plurality of first spacers are formed along the sidewalls of the gate electrode patterns, a first interdielectric layer formed on the entire surface of a resultant in which the first spacers are formed, a plurality of bit line patterns arranged in parallel on the first interdielectric layer to be perpendicular to the gate electrode patterns, in which a plurality of second spacers are formed along the sidewalls of the bit line patterns, a plurality of contacts for bit lines self-aligned with the first spacers, a second interdielectric layer formed on the entire surface of a resultant in which the second spacers are formed, and a plurality of contacts for storage electrodes simultaneously self-aligned with the second and first spacers.

公开(公告)号：US20080280381A1

公开(公告)日：2008-11-13

申请号：US12219214

申请日：2008-07-17

申请人： Doo-youl Lee ,  Gi-sung Yeo ,  Han-ku Cho ,  Jung-hyeon Lee

发明人： Doo-youl Lee ,  Gi-sung Yeo ,  Han-ku Cho ,  Jung-hyeon Lee

IPC分类号： H01L21/66

CPC分类号： H01L22/34 ,  G03F7/40 ,  H01L21/0273

摘要： In a resist reflow measurement key, and method of fabricating a fine pattern of a semiconductor device using the same, the resist reflow measurement key includes a first reflow key including a plurality of first pattern elements each having a first pattern with a first radius of curvature located on a first side of a first center line and a second pattern with a second radius of curvature located on a second side of the first center line, and a second reflow key including a plurality of second pattern elements each having a third pattern with a third radius of curvature located on a first side of a second center line and a fourth pattern with a fourth radius of curvature located on a second side of the second center line, the second reflow key being formed on a same plane of a substrate as the first reflow key.

摘要翻译： 在抗蚀剂回流测量键和使用其的半导体器件的精细图案的制造方法中，抗蚀剂回流测量键包括第一回流键，该第一回流键包括多个第一图案元素，每个第一图案元素具有第一曲率半径 位于第一中心线的第一侧和位于第一中心线的第二侧上的具有第二曲率半径的第二图案，以及第二回流键，包括多个第二图案元素，每个第二图案元素具有第三图案， 位于第二中心线的第一侧上的第三曲率半径和位于第二中心线的第二侧上的具有第四曲率半径的第四图案，第二回流键形成在与第二中心线相同的基板的同一平面上 首先回流钥匙

公开(公告)号：US20080124931A1

公开(公告)日：2008-05-29

申请号：US11978718

申请日：2007-10-30

申请人： Doo-youl Lee ,  Pan-suk Kwak ,  Sung-gon Jung ,  Jung-hyeon Lee ,  Suk-joo Lee ,  Cha-won Koh ,  Ji-young Lee

发明人： Doo-youl Lee ,  Pan-suk Kwak ,  Sung-gon Jung ,  Jung-hyeon Lee ,  Suk-joo Lee ,  Cha-won Koh ,  Ji-young Lee

IPC分类号： H01L21/302

CPC分类号： H01L21/0332 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/31144 ,  H01L21/76816 ,  H01L21/76838

摘要： A method for forming fine patterns of a semiconductor device includes forming an etching film on a substrate having first and second areas, forming first mask patterns on the substrate to have a first pattern density in the first area and a second pattern density in the second area, forming first capping patterns between the first mask patterns, forming second capping patterns between the first mask patterns, such that recess areas are formed between second capping patterns, and such that a first etching pattern is defined to include the first and second capping patterns, forming second mask patterns in the recess areas to include the first and second mask patterns, removing one of the first and second etching patterns, such that a single etching pattern is remaining on the substrate, and etching the etching film using the remaining etching pattern as an etch mask to form etching film patterns.

摘要翻译： 用于形成半导体器件的精细图案的方法包括在具有第一和第二区域的衬底上形成蚀刻膜，在衬底上形成第一掩模图案以在第一区域中具有第一图案密度，在第二区域中形成第二图案密度 在所述第一掩模图案之间形成第一封盖图案，在所述第一掩模图案之间形成第二封盖图案，使得在第二封盖图案之间形成凹陷区域，并且使得第一蚀刻图案被限定为包括所述第一和第二封盖图案， 在凹陷区域中形成第二掩模图案以包括第一和第二掩模图案，去除第一和第二蚀刻图案中的一个，使得在基板上残留单个蚀刻图案，并使用剩余的蚀刻图案蚀刻蚀刻膜作为 蚀刻掩模以形成蚀刻膜图案。

公开(公告)号：US20090274980A1

公开(公告)日：2009-11-05

申请号：US12267687

申请日：2008-11-10

申请人： Yool Kang ,  Suk-joo Lee ,  Jung-hyeon Lee ,  Shi-yong Yi

发明人： Yool Kang ,  Suk-joo Lee ,  Jung-hyeon Lee ,  Shi-yong Yi

IPC分类号： G03F7/20

CPC分类号： H01L21/027 ,  G03F7/0035 ,  G03F7/40 ,  H01L21/0273 ,  H01L21/0338 ,  H01L21/32139

摘要： A method of forming fine patterns of a semiconductor device according to a double patterning process that uses acid diffusion is provided. In this method, a plurality of first mask patterns are formed on a substrate so as to be separated from one another. A capping film including an acid source is formed on sidewalls and an upper surface of each of the plurality of first mask patterns. A second mask layer is formed on the capping films. A plurality of acid diffused regions are formed within the second mask layer by diffusing acid obtained from the acid source from the capping films into the second mask layer. A plurality of second mask patterns are formed of residual parts of the second mask layer which remain in the first spaces after removing the acid diffused regions of the second mask layer.

摘要翻译： 提供了根据使用酸扩散的双重图案化工艺形成半导体器件的精细图案的方法。 在该方法中，在基板上形成多个第一掩模图案以彼此分离。 在多个第一掩模图案的每一个的侧壁和上表面上形成包括酸源的封盖膜。 在封盖膜上形成第二掩模层。 通过将从酸源获得的酸从封盖膜扩散到第二掩模层中，在第二掩模层内形成多个酸扩散区。 多个第二掩模图案由除去第二掩模层的酸扩散区域之后残留在第一间隙中的第二掩模层的残留部分形成。

公开(公告)号：US07205241B2

公开(公告)日：2007-04-17

申请号：US10731931

申请日：2003-12-10

申请人： Chang-min Park ,  Jung-hyeon Lee ,  Han-ku Cho ,  Joon-soo Park

发明人： Chang-min Park ,  Jung-hyeon Lee ,  Han-ku Cho ,  Joon-soo Park

IPC分类号： H01L21/302

CPC分类号： H01L21/76897 ,  H01L21/76895 ,  H01L27/10855 ,  H01L27/10894 ,  H01L28/91 ,  Y10S438/942

摘要： Methods for manufacturing semiconductor devices with contact bodies extended in a direction of a bit line to increase the contact area between a contact body and a storage electrode is provided. In one aspect a method includes forming gate lines on a semiconductor substrate, forming a first insulating layer to cover the gate lines, forming first contact pads and second contact pads, which are electrically connected to the semiconductor substrate between the gate lines, by penetrating the first insulating layer. Further, a second insulating layer is formed to cover the first contact pads and the second contact pads, and bit lines are formed across over the gate lines and are electrically connected to the second contact pads by penetrating the second insulating layer. In addition, a third insulating layer is formed to cover the bit lines and is selectively etched to form a band-type opening that crosses the bit lines and exposes the first contact pads.

摘要翻译： 提供了制造具有沿位线方向延伸的接触体以增加接触体与存储电极之间的接触面积的半导体器件的方法。 在一个方面，一种方法包括在半导体衬底上形成栅极线，形成第一绝缘层以覆盖栅极线，形成第一接触焊盘和第二接触焊盘，这些接触焊盘和第二接触焊盘通过穿透栅极线与半导体衬底电连接 第一绝缘层。 此外，形成第二绝缘层以覆盖第一接触焊盘和第二接触焊盘，并且位线横跨栅极线形成，并且通过穿透第二绝缘层而电连接到第二接触焊盘。 此外，形成第三绝缘层以覆盖位线，并且被选择性地蚀刻以形成穿过位线并暴露第一接触焊盘的带状开口。

公开(公告)号：US20050089776A1

公开(公告)日：2005-04-28

申请号：US10937398

申请日：2004-09-10

申请人： Doo-youl Lee ,  Gi-sung Yeo ,  Han-ku Cho ,  Jung-hyeon Lee

发明人： Doo-youl Lee ,  Gi-sung Yeo ,  Han-ku Cho ,  Jung-hyeon Lee

IPC分类号： G03C5/00 ,  G03F7/40 ,  H01L21/027 ,  H01L21/3205 ,  H01L21/4763 ,  H01L23/544

CPC分类号： H01L22/34 ,  G03F7/40 ,  H01L21/0273

摘要： In a resist reflow measurement key, and method of fabricating a fine pattern of a semiconductor device using the same, the resist reflow measurement key includes a first reflow key including a plurality of first pattern elements each having a first pattern with a first radius of curvature located on a first side of a first center line and a second pattern with a second radius of curvature located on a second side of the first center line, and a second reflow key including a plurality of second pattern elements each having a third pattern with a third radius of curvature located on a first side of a second center line and a fourth pattern with a fourth radius of curvature located on a second side of the second center line, the second reflow key being formed on a same plane of a substrate as the first reflow key.

摘要翻译： 在抗蚀剂回流测量键和使用其的半导体器件的精细图案的制造方法中，抗蚀剂回流测量键包括第一回流键，该第一回流键包括多个第一图案元素，每个第一图案元素具有第一曲率半径 位于第一中心线的第一侧和位于第一中心线的第二侧上的具有第二曲率半径的第二图案，以及第二回流键，包括多个第二图案元素，每个第二图案元素具有第三图案， 位于第二中心线的第一侧上的第三曲率半径和位于第二中心线的第二侧上的具有第四曲率半径的第四图案，第二回流键形成在与第二中心线相同的基板的同一平面上 首先回流钥匙

公开(公告)号：US06492701B1

公开(公告)日：2002-12-10

申请号：US09324072

申请日：1999-06-01

申请人： In-sung Kim ,  Jung-hyeon Lee ,  Han-ku Cho

发明人： In-sung Kim ,  Jung-hyeon Lee ,  Han-ku Cho

IPC分类号： H01L310232

CPC分类号： H01L21/0276 ,  H01L21/28044 ,  H01L21/28061 ,  H01L21/76802

摘要： A semiconductor device including an anti-reflective cap and spacer, a method of manufacturing the same, and a method of forming a photoresist pattern using the same are provided. The semiconductor device according to the present invention includes an anti-reflective cap and an anti-reflective spacer on an upper surface and side walls of a reflective pattern formed on the semiconductor substrate. Therefore, the deformation of the photoresist pattern by the light reflected from the reflective pattern is minimized during a photolithography process.

摘要翻译： 提供了包括抗反射盖和间隔物的半导体器件，其制造方法和使用其形成光致抗蚀剂图案的方法。 根据本发明的半导体器件包括在半导体衬底上形成的反射图案的上表面上的抗反射盖和抗反射隔板。 因此，在光刻工艺中，由反射图案反射的光使光刻胶图案的变形最小化。

公开(公告)号：US07473497B2

公开(公告)日：2009-01-06

申请号：US11084327

申请日：2005-03-18

申请人： In-sung Kim ,  Jung-hyeon Lee ,  Sung-gon Jung

发明人： In-sung Kim ,  Jung-hyeon Lee ,  Sung-gon Jung

IPC分类号： G03F1/00

CPC分类号： G03F1/32 ,  G03F1/36

摘要： A phase shifting mask (PSM) for manufacturing a semiconductor device and a method of fabricating the same includes a transparent substrate, a main pattern formed on the transparent substrate and comprising a first phase shifting layer having a first optical transmittance greater than 0, and at least one assistant pattern formed on the transparent substrate proximal to the main pattern for phase-shifting by the same degree as the main pattern and having a second optical transmittance, which is less than the first optical transmittance.