公开(公告)号：US07473497B2

公开(公告)日：2009-01-06

申请号：US11084327

申请日：2005-03-18

Applicant: In-sung Kim ,  Jung-hyeon Lee ,  Sung-gon Jung

Inventor： In-sung Kim ,  Jung-hyeon Lee ,  Sung-gon Jung

IPC: G03F1/00

CPC classification number: G03F1/32 ,  G03F1/36

Abstract: A phase shifting mask (PSM) for manufacturing a semiconductor device and a method of fabricating the same includes a transparent substrate, a main pattern formed on the transparent substrate and comprising a first phase shifting layer having a first optical transmittance greater than 0, and at least one assistant pattern formed on the transparent substrate proximal to the main pattern for phase-shifting by the same degree as the main pattern and having a second optical transmittance, which is less than the first optical transmittance.

公开(公告)号：US07457058B2

公开(公告)日：2008-11-25

申请号：US11451580

申请日：2006-06-13

Applicant: Woo-Seok Shim ,  Jung-Hyeon Lee ,  Young-Koog Han ,  Kwang-Sub Yoon ,  Si-Hyeung Lee

Inventor： Woo-Seok Shim ,  Jung-Hyeon Lee ,  Young-Koog Han ,  Kwang-Sub Yoon ,  Si-Hyeung Lee

IPC: G02B26/02

CPC classification number: G02B7/00 ,  G03F7/701 ,  G03F7/70825

Abstract: In an optical member holder and a projection exposure apparatus having the same, a light beam radiated from a light source may be formed into light having a desired shape by selecting one of a plurality of optical elements. An optical element holder may include a support member to support the plurality of optical elements, a first driving section to move or rotate the support member to select one of the optical elements, and a second driving section to rotate the selected optical element to adjust an arrangement direction thereof. The light formed by the selected optical element may be directed through a reticle.

Abstract translation: 在具有该光学构件保持器和投影曝光设备的光学构件保持器和投影曝光设备中，从光源辐射的光束可以通过选择多个光学元件之一形成具有所需形状的光。 光学元件保持器可以包括用于支撑多个光学元件的支撑构件，用于移动或旋转支撑构件以选择一个光学元件的第一驱动部分和第二驱动部分，以旋转所选择的光学元件以调整 排列方向。 由所选择的光学元件形成的光可以被引导通过掩模版。

公开(公告)号：US07176512B2

公开(公告)日：2007-02-13

申请号：US10918175

申请日：2004-08-13

Applicant: Jung-Hyeon Lee ,  Gi-Sung Yeo ,  Doo-Hoon Goo ,  Woo-Sung Han

Inventor： Jung-Hyeon Lee ,  Gi-Sung Yeo ,  Doo-Hoon Goo ,  Woo-Sung Han

IPC: H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

CPC classification number: H01L27/10885 ,  H01L27/0207 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/10888 ,  H01L27/10891

Abstract: A semiconductor memory device comprises a plurality of rows, each row comprising a plurality of active regions arranged at a pitch wherein the active regions in adjacent rows are shifted with respect to each other by one half of the pitch, wherein a distance between each active region in a row is equal to a distance between active regions in adjacent rows.

Abstract translation: 半导体存储器件包括多行，每行包括以间距排列的多个有源区，其中相邻行中的有源区相对于间距彼此偏移一半，其中每个有源区之间的距离 在一行中等于相邻行中的活动区域之间的距离。

公开(公告)号：US20060284259A1

公开(公告)日：2006-12-21

申请号：US11449689

申请日：2006-06-09

Applicant: Jung-Hyeon Lee ,  Si-Hyeung Lee ,  Kwang-Sub Yoon ,  Bong-Cheol Kim

Inventor： Jung-Hyeon Lee ,  Si-Hyeung Lee ,  Kwang-Sub Yoon ,  Bong-Cheol Kim

IPC: H01L29/76

CPC classification number: H01L27/0207 ,  H01L27/10817 ,  H01L27/10885

Abstract: In a semiconductor device having asymmetric bit lines and a method of manufacturing the same, a plurality of active regions are electrically isolated from one another by an isolation layer. Each active region extends in a first direction and has a central portion between end portions. The device includes a plurality of transistors, each including first impurity doped regions formed at the central portions and second impurity doped regions formed at both end portions to extend in a second direction different from the first direction. A plurality of asymmetric bit lines are electrically connected to the first impurity doped regions, each extending in a third direction substantially perpendicular to the second direction. Each asymmetric bit line has a first side surface extending in a straight line along the third direction, and a second side surface including a plurality of protrusions.

Abstract translation: 在具有不对称位线的半导体器件及其制造方法中，多个有源区域通过隔离层彼此电隔离。 每个有源区域在第一方向上延伸并且在端部之间具有中心部分。 该器件包括多个晶体管，每个晶体管包括形成在中心部分的第一杂质掺杂区域和形成在两个端部处的第二杂质掺杂区域，以沿与第一方向不同的第二方向延伸。 多个非对称位线电连接到第一杂质掺杂区域，每个第一杂质掺杂区域在基本上垂直于第二方向的第三方向上延伸。 每个不对称位线具有沿着第三方向在直线上延伸的第一侧表面和包括多个突起的第二侧表面。

公开(公告)号：US20050269615A1

公开(公告)日：2005-12-08

申请号：US11015993

申请日：2004-12-17

Applicant: Doo-hoon Goo ,  Jung-hyeon Lee ,  Gi-sung Yeo ,  Han-ku Cho ,  Sang-gyun Woo

Inventor： Doo-hoon Goo ,  Jung-hyeon Lee ,  Gi-sung Yeo ,  Han-ku Cho ,  Sang-gyun Woo

IPC: H01L27/108 ,  H01L21/8242 ,  H01L27/02 ,  H01L29/74

CPC classification number: H01L27/10888 ,  H01L27/0207 ,  H01L27/10814

Abstract: DRAM devices include a plurality of word lines extending in a first direction and a plurality of bit lines extending in a second direction and intersecting the word lines. A plurality of active regions is provided that are electrically coupled to the word lines and the bit lines. Each of the active regions defines a single unit memory cell having an area of 6F2 in terms of a minimum line width F. Each of the active regions may be overlapped by only one word line and the active regions may be defined by an isolation region.

Abstract translation: DRAM装置包括沿第一方向延伸的多个字线和沿第二方向延伸并与字线相交的多个位线。 提供了多个有源区域，其被电耦合到字线和位线。 每个有源区域以最小线宽度F来限定具有6F 2的面积的单个单元存储单元。每个有源区域可以仅由一条字线重叠，并且有源区域 可以由隔离区限定。

公开(公告)号：US06893779B2

公开(公告)日：2005-05-17

申请号：US10008064

申请日：2001-11-05

Applicant: In-sung Kim ,  Jung-hyeon Lee ,  Sung-gon Jung

Inventor： In-sung Kim ,  Jung-hyeon Lee ,  Sung-gon Jung

IPC: G03F1/00 ,  G03F1/29 ,  G03F1/32 ,  G03F1/36 ,  G03F1/54 ,  G03F1/68 ,  G03F1/70 ,  H01L21/027 ,  G03F9/00

CPC classification number: G03F1/32 ,  G03F1/36

Abstract: A phase shifting mask (PSM) for manufacturing a semiconductor device and a method of fabricating the same includes a transparent substrate, a main pattern formed on the transparent substrate and comprising a first phase shifting layer having a first optical transmittance greater than 0, and at least one assistant pattern formed on the transparent substrate proximal to the main pattern for phase-shifting by the same degree as the main pattern and having a second optical transmittance, which is less than the first optical transmittance.

公开(公告)号：US20050070080A1

公开(公告)日：2005-03-31

申请号：US10944151

申请日：2004-09-16

Applicant: Eun-Mi Lee ,  Doo-Hoon Goo ,  Jung-Hyeon Lee ,  Gi-Sung Yeo

Inventor： Eun-Mi Lee ,  Doo-Hoon Goo ,  Jung-Hyeon Lee ,  Gi-Sung Yeo

IPC: H01L21/28 ,  H01L21/4763 ,  H01L21/60 ,  H01L23/485

CPC classification number: H01L21/76897 ,  H01L23/485 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Embodiments of the invention provide methods of forming SAC pads in non-straight semiconductor device having non-straight type or separate type active regions. A plurality of gate line structures extending in one direction may be formed on a semiconductor substrate having non-straight active regions. An interlayer insulating layer covering gate line structures may be formed on the gate line structures. Then, a photo-resist layer may be formed on the interlayer insulating layer. A photo-resist pattern may be formed through exposing and developing the photo-resist layer by using a photo-mask having, for example, a bar type, a wave type, or a reverse active type pattern. Then, contact holes exposing source/drain regions may be formed by etching the interlayer insulating layer using the photo-resist pattern as an etching mask. Contact pads may then be formed by filling the contact holes with a conductive material.

Abstract translation: 本发明的实施例提供了在具有非直型或分离型有源区的非直线半导体器件中形成SAC焊盘的方法。 可以在具有非直线活性区域的半导体衬底上形成沿一个方向延伸的多个栅极线结构。 覆盖栅极线结构的层间绝缘层可以形成在栅极线结构上。 然后，可以在层间绝缘层上形成光致抗蚀剂层。 可以通过使用具有例如棒型，波型或反向活性型图案的光掩模，通过曝光和显影光致抗蚀剂层来形成光致抗蚀剂图案。 然后，可以通过使用光刻胶图案作为蚀刻掩模蚀刻层间绝缘层来形成暴露源极/漏极区的接触孔。 然后可以通过用导电材料填充接触孔来形成接触垫。

公开(公告)号：US06381165B1

公开(公告)日：2002-04-30

申请号：US09966785

申请日：2001-09-28

Applicant: Jung-hyeon Lee ,  Han-ku Cho

Inventor： Jung-hyeon Lee ,  Han-ku Cho

IPC: G11C502

CPC classification number: H01L27/10808 ,  G11C5/025 ,  H01L27/0207

Abstract: A semiconductor memory device that is capable of reducing the probability of a bridge being generated between storage node electrodes, and a mask pattern for defining the storage node electrodes, are provided. The semiconductor memory device includes a plurality of storage node electrodes that are vertically and horizontally arranged a predetermined distance apart in columns and rows, respectively. Among the plurality of storage node electrodes, storage node electrodes belonging to even-numbered columns are shifted up or down a predetermined distance. The shifted storage node electrodes are shifted in a gap between vertically adjacent storage node electrodes belonging to a same column.

Abstract translation: 提供了能够降低在存储节点电极之间产生桥的可能性的半导体存储器件，以及用于限定存储节点电极的掩模图案。 半导体存储器件包括分别沿列和行分别垂直和水平布置成预定距离的多个存储节点电极。 在多个存储节点电极中，属于偶数列的存储节点电极向上或向下移动预定距离。 偏移的存储节点电极在属于同一列的垂直相邻的存储节点电极之间的间隙中偏移。

公开(公告)号：US20080280381A1

公开(公告)日：2008-11-13

申请号：US12219214

申请日：2008-07-17

Applicant: Doo-youl Lee ,  Gi-sung Yeo ,  Han-ku Cho ,  Jung-hyeon Lee

Inventor： Doo-youl Lee ,  Gi-sung Yeo ,  Han-ku Cho ,  Jung-hyeon Lee

IPC: H01L21/66

CPC classification number: H01L22/34 ,  G03F7/40 ,  H01L21/0273

Abstract: In a resist reflow measurement key, and method of fabricating a fine pattern of a semiconductor device using the same, the resist reflow measurement key includes a first reflow key including a plurality of first pattern elements each having a first pattern with a first radius of curvature located on a first side of a first center line and a second pattern with a second radius of curvature located on a second side of the first center line, and a second reflow key including a plurality of second pattern elements each having a third pattern with a third radius of curvature located on a first side of a second center line and a fourth pattern with a fourth radius of curvature located on a second side of the second center line, the second reflow key being formed on a same plane of a substrate as the first reflow key.

Abstract translation: 在抗蚀剂回流测量键和使用其的半导体器件的精细图案的制造方法中，抗蚀剂回流测量键包括第一回流键，该第一回流键包括多个第一图案元素，每个第一图案元素具有第一曲率半径 位于第一中心线的第一侧和位于第一中心线的第二侧上的具有第二曲率半径的第二图案，以及第二回流键，包括多个第二图案元素，每个第二图案元素具有第三图案， 位于第二中心线的第一侧上的第三曲率半径和位于第二中心线的第二侧上的具有第四曲率半径的第四图案，第二回流键形成在与第二中心线相同的基板的同一平面上 首先回流钥匙

公开(公告)号：US20080230929A1

公开(公告)日：2008-09-25

申请号：US12042377

申请日：2008-03-05

Applicant: Jang-ho Shin ,  Chan-hoon Park ,  Jung-Hyeon Lee ,  Suk-joo Lee ,  Hyun-tae Kang ,  Jeong-hee Cho ,  Young-hoon Song

Inventor： Jang-ho Shin ,  Chan-hoon Park ,  Jung-Hyeon Lee ,  Suk-joo Lee ,  Hyun-tae Kang ,  Jeong-hee Cho ,  Young-hoon Song

IPC: H01L23/544

CPC classification number: H01L23/544 ,  H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Provided are an overlay mark of a semiconductor device and a semiconductor device including the overlay mark. The overlay mark includes: reference marks formed in rectangular shapes comprising sides in which fine patterns are formed; and comparison marks formed as rectangular shapes which are smaller than the rectangular shapes of the reference marks and formed of fine patterns, wherein the number of comparison marks is equal to the number of reference marks, wherein the reference marks and the comparison marks are formed on different thin films formed on a semiconductor substrate to be used to inspect alignment states of the different thin films, and the overlay mark reflects an effect of aberration of patterns of memory cells through the fine patterns during a calculation of MR (mis-registration).

Abstract translation: 提供半导体器件的覆盖标记和包括覆盖标记的半导体器件。 覆盖标记包括：形成为包括形成精细图案的侧面的矩形形状的参考标记; 和形成为小于参考标记的矩形形状并由精细图案形成的矩形形状的比较标记，其中比较标记的数量等于参考标记的数量，其中参考标记和比较标记形成在 在半导体衬底上形成的用于检测不同薄膜的取向状态的不同薄膜，并且叠加标记反映了在计算MR（误对准）期间通过精细图案的存储器单元的图案的像差的影响。