公开(公告)号：US09531395B2

公开(公告)日：2016-12-27

申请号：US14044075

申请日：2013-10-02

Applicant: Khalifa University of Science, Technology, and Research ,  British Telecommunications plc ,  Emirates Telecommunications Corporation

Inventor： James Aweya

IPC: H04J3/06 ,  H03L7/197

CPC classification number: H03L7/1976 ,  H03L2207/50 ,  H04J3/0667 ,  H04J3/0697

Abstract: This invention relates to methods and devices for time and frequency synchronization, especially over packet networks using, for example, the IEEE 1588 Precision Time Protocol (PTP). Timing protocol messages are exposed to artifacts in the network such as packet delay variations (PDV) or packet losses. Embodiments of the invention provide a digital phase locked loop (DPLL) based on direct digital synthesis to provide both time and frequency signals for use at the slave (time client). An example of this DPLL in conjunction with a recursive least squares mechanism for clock offset and skew estimation is also provided.

Abstract translation: 本发明涉及用于时间和频率同步的方法和装置，特别是涉及使用例如IEEE 1588精确时间协议（PTP）的分组网络。 定时协议消息暴露在网络中的伪影，例如分组延迟变化（PDV）或分组丢失。 本发明的实施例提供了一种基于直接数字合成的数字锁相环（DPLL），以提供在从机（时间客户机）上使用的时间和频率信号。 还提供了该DPLL与用于时钟偏移和偏移估计的递归最小二乘机制的示例。

公开(公告)号：US20160250749A1

公开(公告)日：2016-09-01

申请号：US15046706

申请日：2016-02-18

Applicant: Khalifa University of Science, Technology and Research

Inventor： Dongming GAN ,  Jian S. DAI ,  Jorge DIAS ,  Rehan UMER ,  Lakmal SENEVIRATNE

IPC: B25J9/00 ,  B29C70/38 ,  B29C70/06 ,  B25J9/16 ,  B25J11/00

CPC classification number: B25J9/006 ,  B25J9/0072 ,  B25J9/1697 ,  B25J11/005 ,  B25J11/0055 ,  B25J11/0075 ,  B29C70/06 ,  B29C70/382 ,  B29C70/386 ,  B29K2101/10 ,  B29K2101/12 ,  B29K2105/06 ,  B29K2105/0881 ,  B29L2031/3076 ,  Y10S901/42 ,  Y10S901/43

Abstract: The present invention introduces a new concept of applying a parallel mechanism in automated fiber placement for aerospace part manufacturing. The proposed system requirements are 4DOF parallel mechanism consisting of two RPS and two UPS limbs with two rotational and two translational motions. Both inverse and forward kinematics models are obtained and solved analytically. Based on the overall Jacobian matrix in screw theory, singularity loci are presented and the singularity-free workspace is correspondingly illustrated. To maximize the singularity-free workspace, locations of the two UPS limbs with the platform and base sizes are used in the optimization which gives a new design of a 4DOF parallel mechanism. A dimensionless Jacobian matrix is also defined and its condition number is used for optimizing the kinematics performance in the optimization process. A numerical example is presented with physical constraint considerations of a test bed design for automated fiber placement.

Abstract translation: 本发明引入了一种在航空航天部件制造的自动光纤放置中应用并联机构的新概念。 所提出的系统要求是由两个RPS和两个具有两个旋转和两个平移运动的两个UPS四肢组成的4DOF并联机构。 分析得到并解决反向和正向运动学模型。 基于螺旋理论中的整体雅可比矩阵，提出了奇异点，并相应地说明了无奇异的工作空间。 为了最大化无奇点的工作空间，在优化中使用具有平台和基座尺寸的两个UPS四肢的位置，给出了4DOF并联机构的新设计。 还定义了无量纲雅可比矩阵，并且其条件数用于优化优化过程中的运动学性能。 给出了一个数字示例，其具有用于自动光纤放置的测试床设计的物理约束考虑。

公开(公告)号：US20160120431A1

公开(公告)日：2016-05-05

申请号：US14926554

申请日：2015-10-29

Applicant: KHALIFA UNIVERSITY OF SCIENCE, TECHNOLOGY, AND RESEARCH

Inventor： Temesghen Tekeste Habte ,  Nourhan Yahya Bayasi ,  Hani Hasan Mustafa Saleh ,  Ahsan Habib Khandoker ,  Baker Mohammad ,  Mahmoud Al-Qutayri ,  Mohammed Ismail Elnaggar

IPC: A61B5/0468 ,  A61B5/04 ,  A61B5/0456

CPC classification number: A61B5/0468 ,  A61B5/02405 ,  A61B5/0245 ,  A61B5/04012 ,  A61B5/0402 ,  A61B5/0428 ,  A61B5/0456 ,  A61B5/0464 ,  A61B5/7264

Abstract: A medical device having automated electrocardiogram (ECG) feature extraction is disclosed. The medical device includes input circuitry configured to receive an ECG signal. Processing circuitry coupled to the input circuitry is configured to identify at least one fiducial point of heartbeat signature of the ECG signal. The processing circuitry is further configured to perform substantially simultaneously both a discrete wavelet transform (DWT) and a curve length transform (CLT) to identify the at least one fiducial point.

Abstract translation: 公开了具有自动心电图（ECG）特征提取的医疗装置。 医疗设备包括被配置为接收ECG信号的输入电路。 耦合到输入电路的处理电路被配置为识别ECG信号的心跳特征的至少一个基准点。 处理电路还被配置为基本同时执行离散小波变换（DWT）和曲线长度变换（CLT）两者以识别至少一个基准点。

公开(公告)号：US20160120430A1

公开(公告)日：2016-05-05

申请号：US14926483

申请日：2015-10-29

Applicant: KHALIFA UNIVERSITY OF SCIENCE, TECHNOLOGY, AND RESEARCH

Inventor： Nourhan Yahya Bayasi ,  Temesghen Tekeste Habte ,  Hani Hasan Mustafa Saleh ,  Ahsan Habib Khandoker ,  Mohammed Ismail Elnaggar

IPC: A61B5/0468 ,  A61B5/0428 ,  A61B5/0245 ,  A61B5/04

CPC classification number: A61B5/0468 ,  A61B5/02405 ,  A61B5/0245 ,  A61B5/04012 ,  A61B5/0402 ,  A61B5/0428 ,  A61B5/0456 ,  A61B5/0464 ,  A61B5/7264

Abstract: A medical device and method for detecting a ventricular arrhythmia event is disclosed. The medical device includes input circuitry configured to receive an electrocardiogram (ECG) signal, processing circuitry coupled to the input circuitry and configured to identify at least one fiducial point of a first heartbeat signature and at least fiducial point of a second heartbeat signature of the ECG signal, and feature extraction circuitry coupled to the processing circuitry. The feature extraction circuitry is configured to determine at least one difference between the at least one fiducial point of the first heartbeat signal and the at least one fiducial point of the second heartbeat signal. Machine learning circuitry is coupled to the feature extraction circuitry and is configured to select a ventricular arrhythmia class based on the at least one difference.

Abstract translation: 公开了一种用于检测室性心律失常事件的医疗装置和方法。 医疗设备包括被配置为接收心电图（ECG）信号的输入电路，耦合到输入电路的处理电路，并且被配置为识别第一心跳标记的至少一个基准点和心电图的第二心跳特征的至少基准点 信号和特征提取电路，其耦合到处理电路。 特征提取电路被配置为确定第一心跳信号的至少一个基准点与第二心跳信号的至少一个基准点之间的至少一个差异。 机器学习电路耦合到特征提取电路，并且被配置为基于至少一个差异来选择心室心律失常类别。

公开(公告)号：US20160070975A1

公开(公告)日：2016-03-10

申请号：US14686905

申请日：2015-04-15

Applicant: Khalifa University of Science, Technology and Research

Inventor： Ehab Najeh Salahat ,  Hani Hasan Mustafa Saleh ,  Andrzej Stefan Sluzek ,  Mohammed Ismail Elnaggar

IPC: G06K9/46 ,  G06K9/52 ,  G06T7/20

CPC classification number: G06K9/4671

Abstract: Architecture for real-time extraction of maximally stable extremal regions (MSERs) is disclosed. The architecture includes communication interface and processing circuitry that is adapted in hardware to receive a data streams of an intensity image and a depth image in real-time and provide intensity labels for image regions within the intensity image that match a given intensity threshold and provide depth labels for image regions within the depth image that match a given depth threshold. The processing circuitry is also adapted in hardware to find intensity extremal regions within the intensity image based upon the intensity labels and to find depth extremal regions within the depth image based upon the depth labels. The processing circuitry determines strong extremal regions based upon significant overlap between the intensity extremal regions and depth extremal regions. The processing circuitry then determines X-MSER ellipses parameters based upon the strong extremal regions and X-MSER criteria.

Abstract translation: 公开了用于实时提取最大稳定极值区域（MSER）的架构。 该架构包括通信接口和处理电路，其适于在硬件中实时地接收强度图像和深度图像的数据流，并且提供与强度图像内匹配给定强度阈值的图像区域的强度标签，并提供深度 在与深度阈值相匹配的深度图像内的图像区域的标签。 处理电路还适用于硬件，以基于强度标签来发现强度图像内的强度极值区域，并且基于深度标签找到深度图像内的深度极值区域。 处理电路基于强度极值区域和深度极值区域之间的显着重叠来确定强极端区域。 处理电路然后基于强极限区域和X-MSER标准确定X-MSER椭圆参数。

公开(公告)号：US09112628B2

公开(公告)日：2015-08-18

申请号：US14044083

申请日：2013-10-02

Applicant: Khalifa University of Science, Technology, and Research ,  British Telecommunications plc ,  Emirates Telecommunications Corporation

Inventor： James Aweya ,  Zdenek Chaloupka

IPC: H04L7/00 ,  H04J3/06

CPC classification number: H04J3/0667

Abstract: This invention relates to methods and devices for compensating for path asymmetry, particularly with reference to time and frequency synchronization. The invention has particular application where time and frequency synchronization over packet networks using, for example, the IEEE 1588 Precision Time Protocol (PTP) is being carried out. Typically communication path delays between a time server (master) and a client (slave) are estimated using the assumption that the forward delay on the path is the same as the reverse delay. As a result, differences between these delays (delay asymmetries) can cause errors in the estimation of the offset of the slave clock from that of the master. Embodiments of the invention provide techniques and devices for compensating for path delay asymmetries that arise when timing protocol messages experience dissimilar queuing delays in the forward and reverse paths.

Abstract translation: 本发明涉及用于补偿路径不对称的方法和装置，特别是参考时间和频率同步。 本发明具有特定的应用，其中使用例如IEEE 1588精确时间协议（PTP）的分组网络进行时间和频率同步。 通常，使用路径上的前向延迟与反向延迟相同的假设来估计时间服务器（主机）和客户机（从机）之间的通信路径延迟。 因此，这些延迟之间的差异（延迟不对称）可能导致从时钟偏移与主器件的偏移的估计误差。 本发明的实施例提供了用于补偿当定时协议消息在正向和反向路径中经历不同的排队延迟时产生的路径延迟不对称的技术和设备。

公开(公告)号：US20150167998A1

公开(公告)日：2015-06-18

申请号：US14104425

申请日：2013-12-12

Applicant: Khalifa University of Science, Technology, and Research ,  Emirates Telecommunications Corporation ,  British Telecommunications plc

Inventor： Fabrice Saffre ,  Mark Shackleton ,  Hanno Hildmann ,  Sébastien Matthieu René Nicolas

IPC: F24F11/00

CPC classification number: F24F11/0009 ,  F24F11/30 ,  F24F11/46

Abstract: This invention relates to methods and systems for controlling consumption, particularly power consumption, more particularly by appliances in a building, and is generally suitable for integration with building management systems. Embodiments of the invention provide methods and systems which probabilistically limit the aggregated power load of a plurality of climate control appliances in a building to a selected value, whilst seeking to minimize the deviation from target environmental conditions within the building. The embodiments of the invention propose distributed decision-making by individual devices based on projected deviation from the target conditions after a period of activity or inactivity.

Abstract translation: 本发明涉及用于控制消耗，特别是功率消耗的方法和系统，特别是建筑物中的设备，并且通常适用于与楼宇管理系统的集成。 本发明的实施例提供了将建筑物中的多个气候控制设备的聚合功率负载概率地限制到选定值的方法和系统，同时寻求使与建筑物内的目标环境条件的偏差最小化。 本发明的实施例提出了在活动或不活动时段之后基于与目标条件的预测偏差的各个设备的分布式决策。

公开(公告)号：US20150167997A1

公开(公告)日：2015-06-18

申请号：US14104416

申请日：2013-12-12

Applicant: Khalifa University of Science, Technology, and Research ,  Emirates Telecommunications Corporation ,  British Telecommunications plc

Inventor： Fabrice Saffre ,  Mark Shackleton ,  Hanno Hildmann ,  Sébastien Matthieu René Nicolas

IPC: F24F11/00

CPC classification number: F24F11/0009 ,  F24F11/30 ,  F24F11/46

Abstract: This invention relates to methods and systems for limiting consumption, particularly power consumption, more particularly by appliances in a building, and is generally suitable for integration with building management systems. Embodiments of the invention provide arrangements in which the aggregated power load of a plurality of appliances is capped to a selected value (which may be arbitrary, or may be dictated by conditions) whilst seeking to minimize the deviation from target environmental conditions within the building through a combination of distributed decision making by the appliances themselves and centralized orchestration, which may be informed by real-time sensor readings and/or known properties of the building. The distributed decision-making by individual devices may be based on projected deviation from the target conditions after a period of activity or inactivity but with a central controller which determines which devices should be switched on.

Abstract translation: 本发明涉及用于限制消耗，特别是功率消耗的方法和系统，特别是建筑物中的设备，并且通常适用于与楼宇管理系统的集成。 本发明的实施例提供了这样的配置，其中多个装置的聚集功率负载被限制到选定值（其可以是任意的，或者可以由条件规定），同时寻求使建筑物内的目标环境条件的偏离最小化， 电器本身的分布式决策和集中式编排的组合，可以通过实时传感器读数和/或建筑物的已知属性来通知。 单个设备的分布式决策可以基于在活动或不活动时段之后的预期偏离目标条件，而是基于确定应该接通哪些设备的中央控制器。

公开(公告)号：US20150092796A1

公开(公告)日：2015-04-02

申请号：US14044068

申请日：2013-10-02

Applicant: Khalifa University of Science, Technology, and Research ,  Emirates Telecommunications Corporation ,  British Telecommunications plc

Inventor： James Aweya

IPC: H04J3/06

CPC classification number: H04J3/0667

Abstract: This invention relates to methods and devices for time and frequency synchronization, especially over packet networks using, for example, the IEEE 1588 Precision Time Protocol (PTP). Timing protocol messages are exposed to artifacts in the network such as packet delay variations (PDV) or packet losses. Embodiments of the invention provide a recursive least squares mechanism for clock offset and skew estimation. A major potential advantage of such estimation is that it does not require knowledge of the statistics of the measurement noise and process noise. An implementation using a digital phase locked loop based on direct digital synthesis to provide both time and frequency signals for use at the slave (time client) is also provided.

Abstract translation: 本发明涉及用于时间和频率同步的方法和装置，特别是涉及使用例如IEEE 1588精确时间协议（PTP）的分组网络。 定时协议消息暴露在网络中的伪影，例如分组延迟变化（PDV）或分组丢失。 本发明的实施例提供了用于时钟偏移和偏差估计的递归最小二乘机制。 这种估计的主要潜在优点是它不需要了解测量噪声和过程噪声的统计。 还提供了使用基于直接数字合成的数字锁相环来提供在从机（时间客户端）使用的时间和频率信号的实现。

公开(公告)号：US20200021378A1

公开(公告)日：2020-01-16

申请号：US16036178

申请日：2018-07-16

Applicant: Khalifa University of Science, Technology, and Research ,  British Telecommunications plc ,  Emirates Telecommunications Corporation

Inventor： James Aweya

IPC: H04J3/06

Abstract: This invention relates to end-to-end transparent clocks and methods of estimating skew in end-to-end transparent clocks. Embodiments of the invention relate to techniques for estimating clock skew between a free-running clock in a transparent clock and a master clock, in particular by using the timing information embedded in timing messages passing through the transparent clock. Further embodiments of the invention set out uses of these estimates to modify the residence times computed by the transparent clock and a synchronization network including such transparent clocks.