公开(公告)号：US07029999B2

公开(公告)日：2006-04-18

申请号：US10750084

申请日：2003-12-30

申请人： Kwan-Yong Lim ,  Byung-Seop Hong ,  Heung-Jae Cho ,  Jung-Ho Lee ,  Jae-Geun Oh ,  Yong-Soo Kim ,  Se-Aug Jang ,  Hong-Seon Yang ,  Hyun-Chul Sohn

发明人： Kwan-Yong Lim ,  Byung-Seop Hong ,  Heung-Jae Cho ,  Jung-Ho Lee ,  Jae-Geun Oh ,  Yong-Soo Kim ,  Se-Aug Jang ,  Hong-Seon Yang ,  Hyun-Chul Sohn

IPC分类号： H01L21/4763 ,  H01L21/44

CPC分类号： H01L21/28061 ,  H01L21/28247

摘要： The present invention is related to a method for fabricating a transistor with a polymetal gate electrode structure. The method includes the steps of: forming a gate insulation layer on a substrate; forming a patterned gate stack structure on the gate insulation layer, wherein the patterned stack structure includes a polysilicon layer as a bottom layer and a metal layer as an upper layer; forming a silicon oxide-based capping layer along a profile containing the patterned gate stack structure and on the gate insulation layer at a predetermined temperature that prevents oxidation of the metal layer; and performing a gate re-oxidation process.

摘要翻译： 本发明涉及一种制造具有多金属栅电极结构的晶体管的方法。 该方法包括以下步骤：在衬底上形成栅极绝缘层; 在所述栅极绝缘层上形成图案化的栅极堆叠结构，其中所述图案化的堆叠结构包括作为底层的多晶硅层和作为上层的金属层; 沿着包含图案化的栅叠层结构的轮廓形成氧化硅基覆盖层，并在预定温度下在栅极绝缘层上形成防止金属层氧化的氧化硅基覆盖层; 并进行栅极再氧化处理。

公开(公告)号：US06979616B2

公开(公告)日：2005-12-27

申请号：US10878346

申请日：2004-06-29

申请人： Se-Aug Jang ,  Heung-Jae Cho ,  Kwan-Yong Lim ,  Hyo-Geun Yoon ,  Seok-Kiu Lee ,  Hyun-Chul Sohn

发明人： Se-Aug Jang ,  Heung-Jae Cho ,  Kwan-Yong Lim ,  Hyo-Geun Yoon ,  Seok-Kiu Lee ,  Hyun-Chul Sohn

IPC分类号： H01L21/31 ,  H01L21/336 ,  H01L21/8239 ,  H01L21/8242 ,  H01L21/8246 ,  H01L27/105

CPC分类号： H01L27/11568 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/10873 ,  H01L27/10894 ,  H01L27/11573

摘要： Disclosed is a method for fabricating a semiconductor device with a dual gate dielectric structure. The method includes the steps of: sequentially forming a first oxide layer, a nitride layer and a second oxide layer on a substrate provided with a cell region for the NVDRAM and a peripheral circuit region for a logic circuit; forming a mask on the cell region; performing a first wet etching process by using the mask as an etch barrier to remove the second oxide layer formed in the peripheral circuit region; performing a second wet etching process by using the second oxide layer remaining in the cell region as an etch barrier to remove the nitride layer formed in the peripheral circuit region; forming a third oxide layer on the first oxide layer remaining in the peripheral circuit region; and forming a gate electrode on the second oxide layer and the third oxide layer.

公开(公告)号：US20050095797A1

公开(公告)日：2005-05-05

申请号：US10879732

申请日：2004-06-30

申请人： Heung-Jae Cho ,  Se-Aug Jang ,  Kwan-Yong Lim

发明人： Heung-Jae Cho ,  Se-Aug Jang ,  Kwan-Yong Lim

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L21/8234 ,  H01L29/49 ,  H01L21/8238

CPC分类号： H01L29/66545 ,  H01L21/28061 ,  H01L21/823437 ,  H01L29/4941 ,  H01L29/6656

摘要： Disclosed is a method for fabricating a semiconductor device with a polymetal gate electrode formed by a partial gate recessing process. The method includes the steps of forming a gate structure including a gate dielectric layer, a polysilicon layer, a metal layer, an etch stop layer and a sacrificial layer sequentially formed on a substrate; selectively performing a re-oxidation process to the gate structure; forming a spacer on each sidewall of the gate structure; implanting ions in the substrate for forming source/drain regions; selectively removing the sacrificial layer of the gate structure to form a recess; and filling an insulating hard mask into the recess for use in a self-aligned contact etching process.

摘要翻译： 公开了一种通过部分栅极凹陷工艺形成的具有多金属栅电极的半导体器件的制造方法。 该方法包括以下步骤：形成栅极结构，该栅极结构包括依次形成在衬底上的栅介电层，多晶硅层，金属层，蚀刻停止层和牺牲层; 选择性地对栅极结构进行再氧化处理; 在所述栅极结构的每个侧壁上形成间隔物; 在衬底中注入离子以形成源/漏区; 选择性地去除栅极结构的牺牲层以形成凹陷; 并将绝缘硬掩模填充到凹槽中以用于自对准接触蚀刻工艺。

公开(公告)号：US08441079B2

公开(公告)日：2013-05-14

申请号：US13043385

申请日：2011-03-08

申请人： Kwan-Yong Lim ,  Hong-Seon Yang ,  Heung-Jae Cho ,  Tae-Kyung Kim ,  Yong-Soo Kim ,  Min-Gyu Sung

发明人： Kwan-Yong Lim ,  Hong-Seon Yang ,  Heung-Jae Cho ,  Tae-Kyung Kim ,  Yong-Soo Kim ,  Min-Gyu Sung

IPC分类号： H01L29/423 ,  H01L29/788

CPC分类号： H01L29/4925 ,  H01L21/28061 ,  H01L29/42324 ,  H01L29/4941 ,  H01L29/513 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device includes a first conductive layer, a first intermediate structure over the first conductive layer, a second intermediate structure over the first intermediate structure, and a second conductive layer over the second intermediate structure. The first intermediate structure includes a metal silicide layer and a nitrogen containing metal layer. The second intermediate structure includes at least a nitrogen containing metal silicide layer.

公开(公告)号：US08319341B2

公开(公告)日：2012-11-27

申请号：US12861679

申请日：2010-08-23

申请人： Min-Gyu Sung ,  Hong-Seon Yang ,  Heung-Jae Cho ,  Yong-Soo Kim ,  Kwan-Yong Lim

发明人： Min-Gyu Sung ,  Hong-Seon Yang ,  Heung-Jae Cho ,  Yong-Soo Kim ,  Kwan-Yong Lim

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L21/28061 ,  H01L21/324 ,  H01L21/823835 ,  H01L21/823842 ,  H01L29/4941

摘要： A gate structure of a semiconductor device includes an intermediate structure, wherein the intermediate structure includes a titanium layer and a tungsten silicide layer. A method for forming a gate structure of a semiconductor device includes forming a polysilicon-based electrode. An intermediate structure, which includes a titanium layer and a tungsten silicide layer, is formed over the polysilicon-based electrode. A metal electrode is formed over the intermediate structure.

摘要翻译： 半导体器件的栅极结构包括中间结构，其中中间结构包括钛层和硅化钨层。 一种用于形成半导体器件的栅极结构的方法包括形成多晶硅基电极。 在多晶硅基电极上形成包括钛层和硅化钨层的中间结构。 在中间结构上形成金属电极。

公开(公告)号：US20120135576A1

公开(公告)日：2012-05-31

申请号：US13242784

申请日：2011-09-23

申请人： Hyun-Jung Lee ,  Young-Pil Kim ,  Jin-Bum Kim ,  Sang-Bom Kang ,  Kwan-Yong Lim

发明人： Hyun-Jung Lee ,  Young-Pil Kim ,  Jin-Bum Kim ,  Sang-Bom Kang ,  Kwan-Yong Lim

IPC分类号： H01L21/336

CPC分类号： H01L29/66545 ,  H01L29/1054 ,  H01L29/66636 ,  H01L29/66651 ,  H01L29/78 ,  H01L29/7848 ,  H01L29/7849

摘要： Provided are a semiconductor device and a method of fabricating a semiconductor device. The method includes providing a substrate having a channel region; forming a gate structure, which comprises a dummy gate pattern, on the substrate; forming first and second trenches by recessing the substrate on both sides of the gate structure, respectively; forming a first semiconductor pattern in the first and second trenches; removing the dummy gate pattern to expose a portion of the channel region; forming a recessed channel region by recessing the portion of the channel region; and forming a second semiconductor pattern in the recessed region.

摘要翻译： 提供半导体器件和制造半导体器件的方法。 该方法包括提供具有沟道区的衬底; 在基板上形成包括虚拟栅极图案的栅极结构; 通过分别在栅极结构的两侧凹陷衬底来形成第一和第二沟槽; 在所述第一和第二沟槽中形成第一半导体图案; 去除伪栅极图案以暴露沟道区域的一部分; 通过使所述通道区域的所述部分凹陷来形成凹陷通道区域; 以及在凹陷区域中形成第二半导体图案。

公开(公告)号：US20120034749A1

公开(公告)日：2012-02-09

申请号：US13197658

申请日：2011-08-03

申请人： Kwan-Yong LIM ,  Chung-Geun Koh ,  Hyun-Jung Lee ,  Tae-Ouk Kwon ,  Seok-Hoon Kim ,  Tae-Ho Cha

发明人： Kwan-Yong LIM ,  Chung-Geun Koh ,  Hyun-Jung Lee ,  Tae-Ouk Kwon ,  Seok-Hoon Kim ,  Tae-Ho Cha

IPC分类号： H01L21/336

CPC分类号： H01L21/823412 ,  H01L21/823807 ,  H01L29/7833 ,  H01L29/7843 ,  H01L29/7847

摘要： A method of manufacturing a semiconductor device can be provided by forming a gate structure on a substrate and forming a diffusion barrier layer on the gate structure and the substrate, A stress layer can be formed on the diffusion barrier layer comprising a metal nitride or a metal oxide having a concentration of nitrogen or oxygen associated therewith. The stress layer can be heated to transform the stress layer into a tensile stress layer to reduce the concentration of the nitrogen or the oxygen in the stress layer. The tensile stress layer and the diffusion barrier layer can be removed.

摘要翻译： 可以通过在衬底上形成栅极结构并在栅极结构和衬底上形成扩散阻挡层来提供制造半导体器件的方法.A应力层可以形成在包含金属氮化物或金属的扩散阻挡层上 具有与其相关联的氮或氧浓度的氧化物。 应力层可以被加热以将应力层转变成拉伸应力层，以减小应力层中的氮或氧的浓度。 可以去除拉伸应力层和扩散阻挡层。

公开(公告)号：US08053841B2

公开(公告)日：2011-11-08

申请号：US12698449

申请日：2010-02-02

申请人： Se-Aug Jang ,  Heung-Jae Cho ,  Kwan-Yong Lim ,  Tae-Yoon Kim

发明人： Se-Aug Jang ,  Heung-Jae Cho ,  Kwan-Yong Lim ,  Tae-Yoon Kim

IPC分类号： H01L21/70

CPC分类号： H01L21/823807 ,  H01L21/823821 ,  H01L21/823842 ,  H01L27/0922 ,  H01L29/66795 ,  H01L29/7851

摘要： A fin transistor includes fin active region, an isolation layer covering both sidewalls of a lower portion of the fin active region, a gate insulation layer disposed over a surface of the fin active region, and a gate electrode disposed over the gate insulation layer and the isolation layer, and having a work function ranging from approximately 4.4 eV to approximately 4.8 eV.

摘要翻译： 翅片晶体管包括翅片有源区，覆盖翅片有源区的下部的两个侧壁的隔离层，设置在翅片有源区的表面上的栅极绝缘层，以及设置在栅极绝缘层和栅极绝缘层上的栅极 隔离层，并且具有范围从约4.4eV至约4.8eV的功函数。

公开(公告)号：US08049268B2

公开(公告)日：2011-11-01

申请号：US12748967

申请日：2010-03-29

申请人： Kwon Hong ,  Kwan-Yong Lim

发明人： Kwon Hong ,  Kwan-Yong Lim

IPC分类号： H01L29/788

CPC分类号： H01L21/28273 ,  H01L29/513 ,  H01L29/7881

摘要： A dielectric structure in a nonvolatile memory device and a method for fabricating the same are provided. The dielectric structure includes: a first oxide layer; a first high-k dielectric film formed on the first oxide layer, wherein the first high-k dielectric film includes one selected from materials with a dielectric constant of approximately 9 or higher and a compound of at least two of the materials; and a second oxide layer formed on the first high-k dielectric film.

摘要翻译： 提供了一种非易失性存储器件中的电介质结构及其制造方法。 介电结构包括：第一氧化物层; 形成在所述第一氧化物层上的第一高k电介质膜，其中所述第一高k电介质膜包括介电常数约为9或更高的材料和至少两种所述材料的化合物中的一种; 以及形成在第一高k电介质膜上的第二氧化物层。

公开(公告)号：US20110256388A1

公开(公告)日：2011-10-20

申请号：US13170662

申请日：2011-06-28

申请人： Kwan-Yong LIM ,  Min-Gyu SUNG ,  Heung-Jae CHO

发明人： Kwan-Yong LIM ,  Min-Gyu SUNG ,  Heung-Jae CHO

IPC分类号： B32B3/00 ,  B32B15/04

CPC分类号： H01L21/76846 ,  H01L27/10885 ,  Y10T428/265 ,  Y10T428/31678

摘要： A semiconductor memory device includes a titanium layer and a titanium nitride layer formed on a substrate, a thin layer formed on the titanium nitride layer, and a metal layer formed on the thin layer, wherein the thin layer increases a grain size of the metal layer.

摘要翻译： 半导体存储器件包括钛基层和形成在衬底上的氮化钛层，形成在氮化钛层上的薄层和形成在薄层上的金属层，其中薄层增加金属层的晶粒尺寸 。