公开(公告)号：US20120034749A1

公开(公告)日：2012-02-09

申请号：US13197658

申请日：2011-08-03

申请人： Kwan-Yong LIM ,  Chung-Geun Koh ,  Hyun-Jung Lee ,  Tae-Ouk Kwon ,  Seok-Hoon Kim ,  Tae-Ho Cha

发明人： Kwan-Yong LIM ,  Chung-Geun Koh ,  Hyun-Jung Lee ,  Tae-Ouk Kwon ,  Seok-Hoon Kim ,  Tae-Ho Cha

IPC分类号： H01L21/336

CPC分类号： H01L21/823412 ,  H01L21/823807 ,  H01L29/7833 ,  H01L29/7843 ,  H01L29/7847

摘要： A method of manufacturing a semiconductor device can be provided by forming a gate structure on a substrate and forming a diffusion barrier layer on the gate structure and the substrate, A stress layer can be formed on the diffusion barrier layer comprising a metal nitride or a metal oxide having a concentration of nitrogen or oxygen associated therewith. The stress layer can be heated to transform the stress layer into a tensile stress layer to reduce the concentration of the nitrogen or the oxygen in the stress layer. The tensile stress layer and the diffusion barrier layer can be removed.

摘要翻译： 可以通过在衬底上形成栅极结构并在栅极结构和衬底上形成扩散阻挡层来提供制造半导体器件的方法.A应力层可以形成在包含金属氮化物或金属的扩散阻挡层上 具有与其相关联的氮或氧浓度的氧化物。 应力层可以被加热以将应力层转变成拉伸应力层，以减小应力层中的氮或氧的浓度。 可以去除拉伸应力层和扩散阻挡层。

公开(公告)号：US20090315091A1

公开(公告)日：2009-12-24

申请号：US12483761

申请日：2009-06-12

申请人： Tae-Ho Cha ,  Seong-Hwee Cheong ,  Jong-Min Baek ,  Jae-Hwa Park ,  Gil-Heyun Choi ,  Byung-Hee Kim ,  Byung-Hak Lee ,  Hee-Sook Park

发明人： Tae-Ho Cha ,  Seong-Hwee Cheong ,  Jong-Min Baek ,  Jae-Hwa Park ,  Gil-Heyun Choi ,  Byung-Hee Kim ,  Byung-Hak Lee ,  Hee-Sook Park

IPC分类号： H01L29/49 ,  H01L27/10

CPC分类号： H01L29/4933 ,  H01L21/28061 ,  H01L27/10873

摘要： A gate structure can include a polysilicon layer, a metal layer on the polysilicon layer, a metal silicide nitride layer on the metal layer and a silicon nitride mask on the metal silicide nitride layer

摘要翻译： 栅极结构可以包括多晶硅层，多晶硅层上的金属层，金属层上的金属硅化物氮化物层和金属硅化物氮化物层上的氮化硅掩模

公开(公告)号：US07528042B2

公开(公告)日：2009-05-05

申请号：US11477090

申请日：2006-06-28

申请人： Kwan-Yong Lim ,  Heung-Jae Cho ,  Dae-Gyu Park ,  Tae-Ho Cha ,  In-Seok Yeo

发明人： Kwan-Yong Lim ,  Heung-Jae Cho ,  Dae-Gyu Park ,  Tae-Ho Cha ,  In-Seok Yeo

IPC分类号： H01L21/336

CPC分类号： H01L21/823462 ,  H01L21/2236 ,  H01L21/28202 ,  H01L21/3144 ,  H01L21/823481 ,  H01L29/518

摘要： A method for forming a dual gate oxide layer, including the steps of: a) forming a gate oxide layer on a semiconductor substrate; and b) increasing a thickness of a part of the gate oxide layer by performing a decoupled plasma treatment. Additional heat processes are not necessary because the dual gate oxide layer is formed with the decoupled plasma. Also, the channel characteristic of the semiconductor device can be ensured because the silicon substrate is not damaged. Furthermore, because the threshold voltage in the cell region is increased without additional channel ion implantation, the electrical characteristic of the semiconductor device can be enhanced.

摘要翻译： 一种形成双栅极氧化层的方法，包括以下步骤：a）在半导体衬底上形成栅极氧化层; 和b）通过执行去耦等离子体处理来增加栅极氧化物层的一部分的厚度。 额外的热处理不是必需的，因为双栅极氧化物层由解耦的等离子体形成。 此外，由于硅衬底没有被损坏，所以可以确保半导体器件的沟道特性。 此外，由于在没有额外的沟道离子注入的情况下单元区域中的阈值电压增加，所以可以提高半导体器件的电特性。

公开(公告)号：US20080093663A1

公开(公告)日：2008-04-24

申请号：US11882654

申请日：2007-08-03

申请人： Jang-hee Lee ,  Gil-Heyun Choi ,  Byung-hee Kim ,  Tae-Ho Cha ,  Hee-Sook Park ,  Geum-Jung Seong

发明人： Jang-hee Lee ,  Gil-Heyun Choi ,  Byung-hee Kim ,  Tae-Ho Cha ,  Hee-Sook Park ,  Geum-Jung Seong

IPC分类号： H01L21/336 ,  H01L29/792

CPC分类号： H01L27/105 ,  H01L27/11568 ,  H01L27/11573

摘要： A method of forming a memory device includes forming a first insulating pattern and a polysilicon pattern in a peripheral region of a substrate, forming a cell gate insulating pattern including a second insulating pattern, a charge storage pattern, and a third insulating pattern in a cell region of the substrate, forming a barrier metal layer on the polysilicon pattern and on the third insulating pattern, forming a conductive layer on the barrier metal layer, patterning the conductive layer to simultaneously form a first conductive pattern on the polysilicon pattern and a second conductive pattern on the third insulating pattern, and patterning the barrier metal layer to simultaneously form a first barrier metal pattern on the polysilicon pattern and a second barrier metal pattern on the third insulating pattern.

摘要翻译： 形成存储器件的方法包括在衬底的周边区域中形成第一绝缘图案和多晶硅图案，在单元中形成包括第二绝缘图案，电荷存储图案和第三绝缘图案的单元栅极绝缘图案 在所述多晶硅图案和所述第三绝缘图案上形成阻挡金属层，在所述阻挡金属层上形成导电层，图案化所述导电层以同时在所述多晶硅图案上形成第一导电图案，并且将第二导电 图案化所述阻挡金属层，同时在所述多晶硅图案上形成第一阻挡金属图案，以及在所述第三绝缘图案上形成第二阻挡金属图案。

公开(公告)号：US20080093660A1

公开(公告)日：2008-04-24

申请号：US11653166

申请日：2007-01-12

申请人： Hee-Sook Park ,  Byung-Hak Lee ,  Tae-Ho Cha ,  Woong-Hee Sohn ,  Jang-Hee Lee ,  Jae-Hwa Park

发明人： Hee-Sook Park ,  Byung-Hak Lee ,  Tae-Ho Cha ,  Woong-Hee Sohn ,  Jang-Hee Lee ,  Jae-Hwa Park

IPC分类号： H01L29/792 ,  H01L21/336

CPC分类号： H01L29/792 ,  H01L29/40114 ,  H01L29/513

摘要： A flash memory device includes a semiconductor substrate, a gate insulating layer having a first width formed on the semiconductor substrate to trap carriers tunneled from the semiconductor substrate and a metal electrode on the gate insulating layer to receive a voltage required for tunneling. The metal electrode having a second width smaller than the first width. The flash memory device further includes a sidewall spacer surrounding a side surface of the metal electrode to prevent oxidation of the metal electrode.

摘要翻译： 闪速存储器件包括半导体衬底，栅极绝缘层，其具有形成在半导体衬底上的第一宽度，以捕获从半导体衬底隧穿的载流子，以及栅极绝缘层上的金属电极，以接收隧道所需的电压。 金属电极的第二宽度小于第一宽度。 闪存器件还包括围绕金属电极的侧表面的侧壁间隔件，以防止金属电极的氧化。

公开(公告)号：US07157339B2

公开(公告)日：2007-01-02

申请号：US10292296

申请日：2002-11-12

申请人： Kwan-Yong Lim ,  Heung-Jae Cho ,  Dae-Gyu Park ,  Tae-Ho Cha ,  In-Seok Yeo

发明人： Kwan-Yong Lim ,  Heung-Jae Cho ,  Dae-Gyu Park ,  Tae-Ho Cha ,  In-Seok Yeo

IPC分类号： H01L21/336

CPC分类号： H01L21/823462 ,  H01L21/2236 ,  H01L21/28202 ,  H01L21/3144 ,  H01L21/823481 ,  H01L29/518

摘要： A method for forming a dual gate oxide layer, including the steps of: a) forming a gate oxide layer on a semiconductor substrate; and b) increasing a thickness of a part of the gate oxide layer by performing a decoupled plasma treatment. Additional heat processes are not necessary because the dual gate oxide layer is formed with the decoupled plasma. Also, the channel characteristic of the semiconductor device can be ensured because the silicon substrate is not damaged. Furthermore, because the threshold voltage in the cell region is increased without additional channel ion implantation, the electrical characteristic of the semiconductor device can be enhanced.

摘要翻译： 一种形成双栅极氧化层的方法，包括以下步骤：a）在半导体衬底上形成栅极氧化层; 和b）通过执行去耦等离子体处理来增加栅极氧化物层的一部分的厚度。 额外的热处理不是必需的，因为双栅极氧化物层由解耦的等离子体形成。 此外，由于硅基板没有被损坏，所以可以确保半导体器件的沟道特性。 此外，由于在没有额外的沟道离子注入的情况下单元区域中的阈值电压增加，所以可以提高半导体器件的电特性。

公开(公告)号：US20060292784A1

公开(公告)日：2006-12-28

申请号：US11424995

申请日：2006-06-19

申请人： Woong Sohn ,  Gil-heyun Choi ,  Chang-won Lee ,  Byung-hee Kim ,  Tae-ho Cha

发明人： Woong Sohn ,  Gil-heyun Choi ,  Chang-won Lee ,  Byung-hee Kim ,  Tae-ho Cha

IPC分类号： H01L21/8238

CPC分类号： H01L21/823462 ,  H01L21/321 ,  H01L21/823437 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/11526 ,  H01L27/11531

摘要： A method of forming an integrated circuit device can include forming a plurality of stacked cell gates in a memory cell region of a semiconductor substrate and a plurality of high-voltage transistor gates in a peripheral circuit region of the semiconductor substrate. The semiconductor substrate including both the plurality of stacked cell gates and the plurality of high-voltage transistor gates is annealed and the annealed semiconductor substrate including both the plurality of stacked cell gates and the plurality of high-voltage transistor gates is plasma oxidized.

摘要翻译： 形成集成电路器件的方法可以包括在半导体衬底的外围电路区域中的半导体衬底的存储单元区域和多个高压晶体管栅极中形成多个堆叠的单元栅极。 包括多个堆叠的单元栅极和多个高压晶体管栅极的半导体基板被退火，并且包括多个堆叠的单元栅极和多个高压晶体管栅极的退火的半导体衬底被等离子体氧化。

公开(公告)号：US06537901B2

公开(公告)日：2003-03-25

申请号：US09887511

申请日：2001-06-25

申请人： Tae Ho Cha ,  Se Aug Jang ,  Tae Kyun Kim ,  Dea Gyu Park ,  In Seok Yeo ,  Jin Won Park

发明人： Tae Ho Cha ,  Se Aug Jang ,  Tae Kyun Kim ,  Dea Gyu Park ,  In Seok Yeo ,  Jin Won Park

IPC分类号： H01L213205

CPC分类号： C23C16/34 ,  C23C14/0641 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/2855 ,  H01L21/28556 ,  H01L21/28562 ,  H01L21/28568 ,  H01L21/823828 ,  H01L29/4958 ,  H01L29/4966

摘要： There is disclosed a method of manufacturing a transistor in a semiconductor device. The present invention forms a Ta film or a TaNx film at a low temperature or forms a first TaNx film in which the composition(x) of nitrogen is 0.45˜0.55, on a gate insulating film in a NMOS region, so that the work function becomes 4.0˜4.4 eV, and also forms a Ta film or a TaNx film at a high temperature or forms a second TaNx film in which the composition(x) of nitrogen is 0.6˜1.4 is formed, on a gate insulating film in a PMOS region, so that the work function becomes 4.8˜5.2 eV. Thus, the present invention can lower the threshold voltage by implementing a surface channel CMOS device both in the NMOS region and the PMOS region.

公开(公告)号：US06506676B2

公开(公告)日：2003-01-14

申请号：US10033509

申请日：2001-12-27

申请人： Dae Gyu Park ,  Tae Ho Cha ,  Se Aug Jang ,  Heung Jae Cho ,  Tae Kyun Kim ,  Kwan Yong Lim ,  In Seok Yeo ,  Jin Won Park

发明人： Dae Gyu Park ,  Tae Ho Cha ,  Se Aug Jang ,  Heung Jae Cho ,  Tae Kyun Kim ,  Kwan Yong Lim ,  In Seok Yeo ,  Jin Won Park

IPC分类号： H01L2144

CPC分类号： H01L21/28194 ,  C23C14/048 ,  C23C16/34 ,  H01L21/28556 ,  H01L21/823842 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/518

摘要： A method of manufacturing semiconductor devices forms a surface channel CMOSFET in the process of manufacturing a metal gate. The method forms a (TixAly)1-zNz film (where z ranges from about 0.0 to about 0.2) having a work function value ranging from about 4.2 to about 4.3 eV on a gate insulating film in a nMOS region, a (TixAly)1-zNz film (where z ranges from about 0.3 to about 0.6) having a work function value ranging from about 4.8 to about 5.0 eV on the gate insulating film in a pMOS region, thus implementing a surface channel CMOS device both in the nMOS region and the pMOS region. Therefore, the threshold voltage is reduced.

摘要翻译： 制造半导体器件的方法在制造金属栅极的过程中形成表面沟道CMOSFET。 该方法在nMOS区域的栅极绝缘膜上形成具有约4.2至约4.3eV的功函数值的（TixAly）1-zNz膜（其中z范围为约0.0至约0.2），（TixAly）1 -zNz膜（其中z范围为约0.3至约0.6），在pMOS区域中的栅极绝缘膜上具有约4.8至约5.0eV的功函数值，从而在nMOS区域和 pMOS区域。 因此，阈值电压降低。

公开(公告)号：US08404576B2

公开(公告)日：2013-03-26

申请号：US13053923

申请日：2011-03-22

申请人： Tae-Ho Cha ,  Seong-Hwee Cheong ,  Gil-Heyun Choi ,  Byung-Hee Kim ,  Hee-Sook Park ,  Jong-Min Baek

发明人： Tae-Ho Cha ,  Seong-Hwee Cheong ,  Gil-Heyun Choi ,  Byung-Hee Kim ,  Hee-Sook Park ,  Jong-Min Baek

IPC分类号： H01L21/283

CPC分类号： H01L29/42324 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/10873 ,  H01L29/4941 ,  H01L29/517

摘要： A gate structure includes an insulation layer on a substrate, a first conductive layer pattern on the insulation layer, a metal ohmic layer pattern on the first conductive layer pattern, a diffusion reduction layer pattern on the metal ohmic layer pattern an amorphous layer pattern on the diffusion reduction layer pattern, and a second conductive layer pattern on the amorphous layer pattern. The gate structure may have a low sheet resistance and desired thermal stability.

摘要翻译： 栅极结构包括在衬底上的绝缘层，绝缘层上的第一导电层图案，第一导电层图案上的金属欧姆层图案，金属欧姆层图案上的扩散减少层图案，其上的非晶层图案 扩散减少层图案和非晶层图案上的第二导电层图案。 栅极结构可以具有低的薄层电阻和期望的热稳定性。