公开(公告)号：US06806530B2

公开(公告)日：2004-10-19

申请号：US10613412

申请日：2003-07-03

Applicant: Kwang-Tae Kim

Inventor： Kwang-Tae Kim

IPC: H01L29788

CPC classification number: H01L27/11521 ,  H01L27/115

Abstract: An EEPROM device and a method of fabricating same. In one aspect, an EEPROM device comprises: a memory transistor including a tunnel insulating layer, first conductive layer patterns, and second conductive layer patterns stacked on a first portion of a semiconductor substrate, and common source regions and floating junction regions arranged at opposite sides of the second conductive layer patterns; and a selection transistor, which is connected to the floating junction regions, and includes a gate insulating layer, the first conductive layer patterns, and the second conductive layer patterns stacked on a second portion of the semiconductor substrate, and drain regions arranged at one side of the second conductive layer patterns opposite the floating junction regions. The first conductive layer patterns in the memory transistor are separated by cell unit and floated, and the insulating layer and the second conductive layer patterns stacked on the first conductive layer patterns are connected to a cell and an adjacent cell, and the first conductive layer patterns and the second conductive layer patterns of the selection transistor are etched and connected by metal plugs. The EEPROM is fabricated using a simplified process which combines a floating gate mask and ion implantation mask into one mask, and which provides reduced resistance by connecting word lines using the metal plugs.

Abstract translation: 一种EEPROM器件及其制造方法。 一方面，一种EEPROM器件包括：存储晶体管，其包括隧道绝缘层，第一导电层图案和层叠在半导体衬底的第一部分上的第二导电层图案，以及布置在相对侧的公共源极区域和浮置接合区域 的第二导电层图案; 以及选择晶体管，其连接到浮置结区域，并且包括栅极绝缘层，第一导电层图案和层叠在半导体衬底的第二部分上的第二导电层图案，以及排列在一侧的漏极区域 的第二导电层图案与浮动结区域相对。 存储晶体管中的第一导电层图案由单元单元分离并浮置，并且堆叠在第一导电层图案上的绝缘层和第二导电层图案连接到单元和相邻单元，并且第一导电层图案 并且选择晶体管的第二导电层图案被金属插塞蚀刻和连接。 使用将浮栅掩模和离子注入掩模组合成一个掩模的简化工艺制造EEPROM，并且通过使用金属插头连接字线来提供降低的电阻。

公开(公告)号：US08922529B2

公开(公告)日：2014-12-30

申请号：US13398903

申请日：2012-02-17

Applicant: Kwang-tae Kim

Inventor： Kwang-tae Kim

IPC: G06F3/043 ,  G09G5/00 ,  G06F3/041

CPC classification number: G06F3/0433 ,  G06F3/043

Abstract: A touch sensor system using vibration at touch point is provided, which includes a first sensor bar having a piezoelectric grid formed on a side surface thereof, a second sensor unit having a piezoelectric grid formed on a side surface thereof, and connected at one end to an end of the first sensor bar in a perpendicular relation, a signal processing unit connected to the first and second sensor units to receive an electric signal, and a touch point calculating unit which calculates a location of touch with respect to a screen through which the touch is inputted, based on the electric signal received at the signal processing unit.

Abstract translation: 提供了一种在接触点处使用振动的触摸传感器系统，其包括在其侧表面上形成有压电栅格的第一传感器棒，具有形成在其侧表面上的压电栅格的第二传感器单元，并且一端连接到 垂直关系的第一传感器杆的端部，连接到第一和第二传感器单元以接收电信号的信号处理单元，以及触摸点计算单元，其计算相对于屏幕的触摸位置， 基于在信号处理单元处接收的电信号输入触摸。

公开(公告)号：US20120110657A1

公开(公告)日：2012-05-03

申请号：US13383996

申请日：2010-07-14

Applicant: Kyung Wan Kang ,  Kwang Tae Kim ,  Heean Park

Inventor： Kyung Wan Kang ,  Kwang Tae Kim ,  Heean Park

IPC: G06F21/20 ,  G06F15/16

CPC classification number: H04L63/0236

Abstract: The invention relates to an apparatus for host-based network separation, comprising: a network separation switch which, when a process is being executed on a host computer, checks whether the network allocated to the process is an internal network or an external network in accordance with the network access authority allocated to the process, and separates the process by IPs allocated to each network; and a packet processor which blocks the access of packet data when the packet data of the process separated by IPs by the network separation switch access a network other than the network to which the relevant IP is allocated.

Abstract translation: 本发明涉及一种用于基于主机的网络分离的装置，包括：网络分离交换机，当在主计算机上执行进程时，检查分配给该进程的网络是否是内部网络或外部网络 将网络访问权限分配给进程，并将进程分配给每个网络的IP; 以及分组处理器，当由网络分离交换机由IP分离的进程的分组数据访问除了相关IP所分配的网络之外的网络时，阻止分组数据的访问。

公开(公告)号：USD610879S1

公开(公告)日：2010-03-02

申请号：US29337811

申请日：2009-05-29

Applicant: Kwang-Tae Kim

Designer： Kwang-Tae Kim

公开(公告)号：US20080197401A1

公开(公告)日：2008-08-21

申请号：US12026812

申请日：2008-02-06

Applicant: Eun-Mi Hong ,  Kwang-Tae Kim ,  Ji-Hoon Park

Inventor： Eun-Mi Hong ,  Kwang-Tae Kim ,  Ji-Hoon Park

IPC: H01L27/105 ,  H01L21/28

CPC classification number: H01L21/28273 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/42324 ,  H01L29/7881

Abstract: A method of manufacturing a nonvolatile memory device is provided. The method includes forming an isolation layer in a semiconductor substrate defining an active region and forming a molding pattern on the isolation layer. A first conductive layer is formed on a sidewall and a top surface of the molding pattern and on the semiconductor substrate. The first conductive layer on the top surface of the molding pattern is selectively removed forming a conductive pattern. The conductive pattern includes a body plate disposed on the active region and a protrusion which extends from an edge of the body plate onto the sidewall of the molding pattern. The molding pattern is then removed. An inter-gate dielectric layer is formed on the isolation layer and the conductive pattern. Nonvolatile memory devices manufactured using the method are also provided.

Abstract translation: 提供一种制造非易失性存储器件的方法。 该方法包括在限定活性区域的半导体衬底中形成隔离层并在隔离层上形成模制图案。 第一导电层形成在模制图案的侧壁和顶表面上以及半导体衬底上。 选择性地去除模制图案的顶表面上的第一导电层，形成导电图案。 导电图案包括设置在有源区域上的主体板和从主体板的边缘延伸到模制图案的侧壁上的突起。 然后移除模制图案。 在隔离层和导电图案上形成栅极间电介质层。 还提供了使用该方法制造的非易失性存储器件。

公开(公告)号：US07352026B2

公开(公告)日：2008-04-01

申请号：US10997835

申请日：2004-11-24

Applicant: Weon-ho Park ,  Byoung-ho Kim ,  Hyun-khe Yoo ,  Seung-beom Yoon ,  Sung-chul Park ,  Ju-ri Kim ,  Kwang-tae Kim ,  Jeong-wook Han

Inventor： Weon-ho Park ,  Byoung-ho Kim ,  Hyun-khe Yoo ,  Seung-beom Yoon ,  Sung-chul Park ,  Ju-ri Kim ,  Kwang-tae Kim ,  Jeong-wook Han

IPC: H01L29/788 ,  H01L29/76

CPC classification number: H01L27/11524 ,  H01L27/105 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11546

Abstract: Provided are an EEPROM cell, an EEPROM device, and methods of manufacturing the EEPROM cell and the EEPROM device. The EEPROM cell is formed on a substrate including a first region and a second region. A first EEPROM device having a first select transistor and a first memory transistor is disposed in the first region, while a second EEPROM device having a second select transistor and a second memory transistor is disposed in the second region. In the first region, a first drain region and a second floating region are formed apart from each other. In the second region, a second drain region and a second floating region are formed apart from each other. A first impurity region, a second impurity region, and a third impurity region are disposed in a common source region between the first and second regions of the substrate. The first and third impurity regions form a DDD structure, and the first and second impurity region form an LDD structure. That is, the first impurity region completely surrounds the second and third impurity regions in horizontal and vertical directions, the second impurity region surrounds the third impurity region in a horizontal direction, and the junction depth of the third impurity is greater than that of the second impurity region.

公开(公告)号：US20060008985A1

公开(公告)日：2006-01-12

申请号：US11171706

申请日：2005-06-30

Applicant: Weon-Ho Park ,  Tea-Kwang Yu ,  Kyoung-Hwan Kim ,  Kwang-Tae Kim

Inventor： Weon-Ho Park ,  Tea-Kwang Yu ,  Kyoung-Hwan Kim ,  Kwang-Tae Kim

IPC: H01L21/336

CPC classification number: H01L21/28273 ,  G11C16/0433 ,  H01L27/11524

Abstract: A method of forming a tunneling insulating layer having a size smaller than the size obtained by the resolution of a photolithography process is provided. The method includes the steps of forming a first insulating layer and a second insulating layer on a substrate, forming a re-flowable material layer pattern to re-flow the re-flowable material layer pattern, removing the second insulating layer and the first insulating layer to expose the substrate, and forming a tunneling insulating layer.

Abstract translation: 提供一种形成尺寸小于通过光刻工艺的分辨率获得的尺寸的隧道绝缘层的方法。 该方法包括在基板上形成第一绝缘层和第二绝缘层的步骤，形成可再流动的材料层图案以再流动可再流动的材料层图案，去除第二绝缘层和第一绝缘层 露出基板，形成隧道绝缘层。

公开(公告)号：US5733387A

公开(公告)日：1998-03-31

申请号：US776806

申请日：1997-02-04

Applicant: Yong Deuk Lee ,  Kwang Tae Kim ,  Bong Un Kim ,  Yong Heon Lee

Inventor： Yong Deuk Lee ,  Kwang Tae Kim ,  Bong Un Kim ,  Yong Heon Lee

IPC: C21D8/00 ,  C21D8/02 ,  C22C38/00 ,  C22C38/44 ,  C22C38/58

CPC classification number: C21D8/0226 ,  C21D8/005 ,  C22C38/001 ,  C22C38/44 ,  C21D2211/001 ,  C21D2211/005 ,  C21D8/021 ,  C21D8/0263

Abstract: A duplex stainless steel consisting of a ferrite phase and an austenite phase is disclosed which is superior in the hot ductility, the high temperature oxidation resistance, the corrosion resistance and the impact toughness. The duplex stainless steel is applied to marine facility and the like. The duplex stainless steel which consists of a ferrite phase and an austenite phase is composed of in weight %: less than 0.03% of C, less than 1.0% of Si, less than 2.0% of Mn, less than 0.04% of P, less than 0.004% of S, less than 2.0% of Cu, 5.0-8.0% of Ni, 22-27% of Cr, 1.0-2.0% of Mo, 2.0-5.0% of W, and 0.13-0.30% of N. Or there are further added one or two elements selected from a group consisting of: less than 0.03% of Ca, less than 0.1% of Ce, less than 0.005% of B and 0.5% of Ti. Further, the ratio (Cr.sub.eq /Ni.sub.eq) of the Cr equivalent (Cr.sub.eq) to the Ni equivalent (Ni.sub.eq) is 2.2-3.0. Further, the weight ratio (W/Mo) of the W to Mo is 2.6-3.4. That is, the duplex stainless steel of the present invention satisfies the above condition, and the Ni.sub.eq and Cr.sub.eq are defined as follows: Ni.sub.eq =%Ni+30.times.%C+0.5.times.%Mn+0.33.times.%Cu+30.times.(%N-0.045), Cr.sub.eq =%Cr+Mo+1.5.times.%Si+0.73.times.%W.

Abstract translation: PCT No.PCT / KR96 / 00084 Sec。 371日期1997年2月4日 102（e）1997年2月4日PCT PCT 1996年6月5日PCT公布。 第WO96 / 39543号公报 日期：1996年12月12日公开了一种由铁素体相和奥氏体相组成的双相不锈钢，其在热延展性，耐高温氧化性，耐腐蚀性和冲击韧性方面优异。 双相不锈钢应用于海洋设施等。 由铁素体相和奥氏体相组成的双相不锈钢由重量％组成：小于0.03的C，小于1.0的Si，小于2.0的Mn，小于0.04的P，少 超过0.004％的S，小于2.0％的Cu，5.0-8.0％的Ni，22-27％的Cr，1.0-2.0％的Mo，2.0-5.0％的W和0.13-0.30％的N.或者 进一步添加一种或两种选自以下的元素：小于0.03％的Ca，小于0.1％的Ce，小于0.005％的B和0.5％的Ti。 此外，Cr当量（Creq）与Ni当量（Nieq）的比（Creq / Nieq）为2.2-3.0。 此外，W与Mo的重量比（W / Mo）为2.6〜3.4。 也就是说，本发明的双相不锈钢满足上述条件，Nieq和Creq定义如下：Nieq =％Ni + 30x％C + 0.5x％Mn + 0.33x％Cu + 30x（％ 0.045），Creq =％Cr + Mo + 1.5×Si + 0.73×W。

公开(公告)号：US4933465A

公开(公告)日：1990-06-12

申请号：US292536

申请日：1988-12-30

Applicant: Kwang-tae Kim ,  Young-soo Kim ,  Jin-youl Kim

Inventor： Kwang-tae Kim ,  Young-soo Kim ,  Jin-youl Kim

IPC: C07D231/52 ,  G03C7/384

CPC classification number: G03C7/384 ,  C07D231/52

Abstract: A magenta color - forming coupler represented by the formula (1) for use in color photographic silver halide photosensitive material: ##STR1## wherein X is halogen; l is 0, 1, 2, or 3; Y is hydrogen or halogen; Q is --NH-- or --NHCO--; n is 1, 2, or 3; K is O, S, or SO.sub.2 ; A is ##STR2## or ##STR3## in which R.sup.1 represents C.sub.1 -C.sub.8 alkylene or phenylene, R.sup.2 represents C.sub.1`-C.sub.4 alkylene or phenylene and q is 1, 2, or 3; R.sup.3 is C.sub.1 -C.sub.8 alkylene; R.sup.4 is C.sub.1 -C.sub.8 alkyl; and m is an integer of 0, 1, or 2, provided that a plurality of R.sup.4 are the same or different each other when m is 2, and a photographic photosensitive material containing the magenta coupler above.

Abstract translation: 用于彩色照相卤化银感光材料的由式（1）表示的品红色成色剂：其中X是卤素; l为0,1,2或3; Y是氢或卤素; Q是-NH-或-NHCO-; n为1,2或3; K是O，S或SO 2; A为或，其中R1表示C1-C8亚烷基或亚苯基，R2表示C1'-C4亚烷基或亚苯基，q为1,2或3; R3是C1-C8亚烷基; R4是C1-C8烷基; m为0，1或2的整数，条件是当m为2时，多个R 4相同或不同，以及含有品红色成色剂的感光感光材料。