公开(公告)号：US20250089318A1

公开(公告)日：2025-03-13

申请号：US18954114

申请日：2024-11-20

Applicant: Micron Technology, Inc.

Inventor： Manuj Nahar ,  Vassil N. Antonov ,  Kamal M. Karda ,  Michael Mutch ,  Hung-Wei Liu ,  Jeffery B. Hull

IPC: H01L29/08 ,  H01L21/02 ,  H01L29/04 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78

Abstract: A transistor comprises a top source/drain region, a bottom source/drain region, a channel region vertically between the top and bottom source/drain regions, and a gate operatively laterally-adjacent the channel region. The channel region is crystalline and comprises a plurality of vertically-elongated crystal grains that individually are directly against both of the top source/drain region and the bottom source/drain region. Other embodiments, including methods, are disclosed.

公开(公告)号：US20250089233A1

公开(公告)日：2025-03-13

申请号：US18784176

申请日：2024-07-25

Applicant: Micron Technology, Inc.

Inventor： Yongjun J. Hu

IPC: H10B12/00

Abstract: Systems, methods and apparatus are provided for nitride lattice support structures and double side capacitors in vertical three-dimensional (3D) memory. An example method includes a method for forming a nitride lattice support structures for an array of vertically stacked memory cells having access devices and storage nodes. The method includes depositing alternating layers of a channel material and a first sacrificial material in repeating iterations to form a vertical stack on a substrate. The vertical stack can be patterned to form a plurality of elongated vertical columns separated by a plurality of first vertical opening. A second sacrificial material can be deposited to fill the first vertical openings and cover the vertical stack. A plurality of vertical openings and lateral recesses can be formed. A nitride material can be deposited in the vertical openings and lateral recesses to form a plurality of nitride lattice support structures.

公开(公告)号：US20250088200A1

公开(公告)日：2025-03-13

申请号：US18958870

申请日：2024-11-25

Applicant: Micron Technology, Inc.

Inventor： Steven J. Baumgartner ,  Neeraj Savla

IPC: H03M1/78 ,  H03F3/45

Abstract: Various embodiments of the present disclosure relate to apparatuses and methods for control loop circuitry. An interface circuit can comprise a digital to analog converter (DAC) configured to provide a differential output signal, a first control loop portion configured to receive a gain reference voltage and to output a first bias voltage to the DAC; and a second control loop portion configured to receive a common mode voltage of a differential input signal and to output a second bias voltage to the DAC.

公开(公告)号：US20250087275A1

公开(公告)日：2025-03-13

申请号：US18768970

申请日：2024-07-10

Applicant: Micron Technology, Inc.

Inventor： Shyam Sunder Raghunathan ,  Yingda Dong ,  Akira Goda

IPC: G11C16/16 ,  G11C16/04 ,  G11C16/28

Abstract: An apparatus can comprise a memory array comprising a plurality of strings of memory cells. A first string of the plurality of strings can comprises: a first group of memory cells coupled to a first group of access lines and corresponding to a first erase block; and a second group of memory cells coupled to a second group of access lines and corresponding to a second erase block. A controller is coupled to the memory array and configured to, in order to selectively erase the second erase block independently of the first erase block: apply a voltage having a first value to a sense line coupled to the plurality of strings; apply a voltage having a second value less than the first value to the first group of access lines; and apply a voltage having a third value less than the second value to the second group of access lines.

公开(公告)号：US20250087266A1

公开(公告)日：2025-03-13

申请号：US18890171

申请日：2024-09-19

Applicant: Micron Technology, Inc.

Inventor： Ferdinando Bedeschi

IPC: G11C13/00 ,  G11C16/04 ,  H10B43/20

Abstract: Methods, systems, and devices for multiple transistor architecture for three-dimensional memory arrays are described. A memory device may include conductive pillars coupled with an access line using two transistors positioned between the conductive pillar and the access line. As part of an access operation for a memory cell coupled with the conductive pillar, the memory device may be configured to bias the access line to a first voltage and activate the two transistors using a second voltage to couple the conductive pillar with the access line. Additionally, the memory device may be configured to bias a gate of a first transistor and a gate of a second transistor coupling an unselected conductive pillar with the access line to a third and fourth voltage, respectively, which may deactivate at least one of the first or second transistor during the access operation and isolate the unselected conductive pillar from the access line.

公开(公告)号：US20250087249A1

公开(公告)日：2025-03-13

申请号：US18811059

申请日：2024-08-21

Applicant: Micron Technology, Inc.

Inventor： Toru Tanzawa

IPC: G11C5/06 ,  G11C5/02 ,  G11C7/12 ,  G11C7/22 ,  G11C16/04 ,  G11C16/06 ,  G11C16/08 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26 ,  H10B41/20 ,  H10B41/35 ,  H10B41/41

Abstract: Apparatuses and methods for interconnections for 3D memory are provided. One example apparatus can include a stack of materials including a plurality of pairs of materials, each pair of materials including a conductive line formed over an insulation material. The stack of materials has a stair step structure formed at one edge extending in a first direction. Each stair step includes one of the pairs of materials. A first interconnection is coupled to the conductive line of a stair step, the first interconnection extending in a second direction substantially perpendicular to a first surface of the stair step.

公开(公告)号：US20250086058A1

公开(公告)日：2025-03-13

申请号：US18954008

申请日：2024-11-20

Applicant: Micron Technology, Inc.

Inventor： Priya Venkataraman ,  Pitamber Shukla ,  Vipul Patel ,  Scott A. Stoller

IPC: G06F11/10 ,  G06F3/06 ,  G06F11/07 ,  G06F12/0882 ,  G11C16/34 ,  G11C29/04 ,  G11C29/44

Abstract: Read calibration by sector of memory can include reading a page of memory, having more than one sector, with a read level, such as a default read level. In response to an error, such as an uncorrectable error correction code read result, the respective read level can be calibrated for each sector to yield a respective calibrated read level per sector. The page of memory can be read with the respective calibrated read level per sector. The calibrated read levels can be stored.

公开(公告)号：US20250085876A1

公开(公告)日：2025-03-13

申请号：US18783121

申请日：2024-07-24

Applicant: Micron Technology, Inc.

Inventor： Douglas Eugene Majerus ,  Cheng Long Ben ,  Qisong Lin

IPC: G06F3/06

Abstract: A memory device includes a boot block that stores boot block code encoded using an encoding scheme. The boot block code includes a set of machine-readable instructions for booting the memory sub-system. A read command directed at the boot block is received while the memory device is in a boot state. Based on the command, the encoded boot block code is read from the boot block and decoded based on the encoding scheme. The decoded boot block code is provided to a memory sub-system controller responsive to the command

公开(公告)号：US20250085859A1

公开(公告)日：2025-03-13

申请号：US18955554

申请日：2024-11-21

Applicant: Micron Technology, Inc.

Inventor： Emanuele Confalonieri ,  Antonino Caprí ,  Nicola Del Gatto ,  Federica Cresci ,  Massimiliano Turconi

IPC: G06F3/06

Abstract: An apparatus can include a plurality of memory devices and a memory controller coupled to the plurality of memory devices via a plurality of memory channels. The plurality of memory channels can be each organized as a plurality of channel groups that can be operated as independent RAS channels (e.g., channels for independent RAS accesses). Data received at the memory controller via different memory channels of one RAS channel can be aligned at various circuits and/or components of the memory controller.

公开(公告)号：US12250818B2

公开(公告)日：2025-03-11

申请号：US17586682

申请日：2022-01-27

Applicant: Micron Technology, Inc.

Inventor： Pei Qiong Cheung ,  Zhixin Xu ,  Yuan Fang

IPC: H10B43/27 ,  H10B43/10

Abstract: Some embodiments include a method of forming an assembly. A first stack of alternating first and second tiers is formed over a conductive structure. A first opening is formed to extend through the first stack. A sidewall of the first opening is lined with a first liner material. The first liner material is converted to a first charge-blocking material. Sacrificial material is formed within the first opening. A second stack of alternating third and fourth tiers is formed over the first stack. A second opening is formed to extend through the second stack to the sacrificial material. A second liner material is formed within the second opening, is anisotropically etched, and is then converted to a second charge-blocking material. The sacrificial material is removed. Charge-storage material, dielectric material and channel material are formed adjacent to the charge-blocking material. Some embodiments include integrated assemblies.