公开(公告)号：US07133819B1

公开(公告)日：2006-11-07

申请号：US09783246

申请日：2001-02-13

Applicant: Michael D. Hutton

Inventor： Michael D. Hutton

IPC: G06F17/50 ,  H03K17/50 ,  H03K19/00

CPC classification number: G06F17/5072 ,  G06F17/5031

Abstract: Provided is a method for estimating delay data comprising receiving an electronic representation of a source electronic design, estimating the criticality of connections which have not yet been placed across a boundary based on statistical data received from at least one other design and revising the design in a manner that biases the design towards a state in which connections with the highest criticality have their delays minimized. A statistical estimate is generated for uncut connections on a path in a partially placed source design comprising receiving at least one source design, partitioning the design, and generating statistical data corresponding to each type of partitioning cut.

Abstract translation: 提供了一种用于估计延迟数据的方法，包括接收源电子设计的电子表示，基于从至少一个其他设计接收的统计数据估计尚未跨越边界的连接的关键性，并且修改设计在 将设计偏向于具有最高关键性的连接将其延迟最小化的状态。 对部分放置的源设计中的路径上的未切割连接生成统计估计，包括接收至少一个源设计，划分设计，以及生成对应于每种类型的分区划分的统计数据。

公开(公告)号：US07120883B1

公开(公告)日：2006-10-10

申请号：US10446650

申请日：2003-05-27

Applicant: Babette van Antwerpen ,  Michael D. Hutton ,  Gregg Baeckler ,  Richard Yuan

Inventor： Babette van Antwerpen ,  Michael D. Hutton ,  Gregg Baeckler ,  Richard Yuan

IPC: G06F17/50

CPC classification number: G06F17/5054 ,  G06F17/5045

Abstract: An electronic automation system performs register retiming on a logic design, which may be a logic design for a programmable logic integrated circuit. Register retiming is a moving or rearranging of registers across combinatorial logic in a design in order to improve a maximum operating frequency or fmax. In one implementation, the system includes machine-readable code, which may be stored on a computer-readable medium such as a disk, executing on a computer. The system balances timing in order to trade off delays between critical and noncritical paths. Register retiming may make changes to a design at a gate level.

公开(公告)号：US06747480B1

公开(公告)日：2004-06-08

申请号：US10195209

申请日：2002-07-12

Applicant: Sinan Kaptanoglu ,  Michael D. Hutton ,  James Schleicher

Inventor： Sinan Kaptanoglu ,  Michael D. Hutton ,  James Schleicher

IPC: H03K19177

CPC classification number: H03K19/17748 ,  H03K19/1737 ,  H03K19/17736

Abstract: A programmable logic integrated circuit device has a plurality of regions of programmable logic disposed on the device in a plurality of intersecting rows and columns of such regions. The regions of logic may include logic subregions that each have a look-up table. Interconnection resources (e.g., inter-region and intra-region interconnection conductors, signal buffers and drivers, programmable connectors, etc.) are provided on the device for making programmable interconnections between the look-up tables. Programmable bidirectional cascade circuitry that is distinct from the interconnections may be used to make connections directly from the output of one look-up table to another without using the interconnection resources. The programmable cascade circuitry may be programmed so that multiple look-up tables are interconnected to form sequential cascade chains or cascade trees.

Abstract translation: 可编程逻辑集成电路器件具有多个可编程逻辑区域，该多个可编程逻辑区域设置在该区域的多个相交行和列中的该器件上。 逻辑区域可以包括各自具有查找表的逻辑子区域。 在设备上提供互连资源（例如，区域间和区域内互连导体，信号缓冲器和驱动器，可编程连接器等），用于在查找表之间进行可编程互连。 与互连不同的可编程双向级联电路可用于使连接从一个查找表的输出直接连接到另一个查找表，而不使用互连资源。 可编程级联电路可以被编程，使得多个查找表互连以形成顺序级联链或级联树。

公开(公告)号：US09705506B2

公开(公告)日：2017-07-11

申请号：US13613925

申请日：2012-09-13

Applicant: Michael D. Hutton ,  James G. Schleicher, II ,  Daniel R. Mansur

Inventor： Michael D. Hutton ,  James G. Schleicher, II ,  Daniel R. Mansur

IPC: H03K19/177

CPC classification number: H03K19/17744 ,  H03K19/17732 ,  H03K19/17796

Abstract: A field programmable gate array (“FPGA”) is provided having integrated application specific integrated circuit (“ASIC”) fabric. The ASIC fabric may be used to implement one or more custom or semi-custom hard blocks within the FPGA. The ASIC fabric can be made up of a “custom region” and an “interface region.” The custom region can implement the custom or semi-custom ASIC design and the interface region can integrate and connect the custom region to the rest of the FPGA circuitry. The custom region may be based on a structured ASIC design. The interface region may allow the ASIC fabric to be incorporated within the hierarchical organization of the FPGA, allowing the custom region to connect to the FPGA circuitry in a seamless manner.

公开(公告)号：US08640067B1

公开(公告)日：2014-01-28

申请号：US12807960

申请日：2010-09-17

Applicant: Michael D. Hutton ,  David Lewis

Inventor： Michael D. Hutton ,  David Lewis

IPC: G06F17/50

CPC classification number: G06F17/5027 ,  G06F17/5054 ,  G06F2217/62

Abstract: A skew generator unit includes a delay chain. The delay chain is coupled to a clock line that transmits a clock signal. The delay chain generates a skewed clock signal having a unit of delay from the clock signal. The skew generator unit also includes a selector. The selector is coupled to the delay chain and the clock line and may select one of the clock signal and the skewed clock signal.

Abstract translation: 偏斜发生器单元包括延迟链。 延迟链耦合到发送时钟信号的时钟线。 延迟链产生具有来自时钟信号的延迟单位的偏斜时钟信号。 偏斜发生器单元还包括选择器。 选择器耦合到延迟链和时钟线，并且可以选择时钟信号和偏斜时钟信号之一。

公开(公告)号：US08402408B1

公开(公告)日：2013-03-19

申请号：US13338776

申请日：2011-12-28

Applicant: Babette van Antwerpen ,  Michael D. Hutton ,  Gregg Baeckler ,  Richard Yuan

Inventor： Babette van Antwerpen ,  Michael D. Hutton ,  Gregg Baeckler ,  Richard Yuan

IPC: G06F17/50

CPC classification number: G06F17/5054 ,  G06F17/5045

Abstract: An electronic automation system performs register retiming on a logic design, which may be a logic design for a programmable logic integrated circuit. Register retiming is a moving or rearranging of registers across combinatorial logic in a design in order to improve a maximum operating frequency or fmax. In one implementation, the system includes machine-readable code, which may be stored on a computer-readable medium such as a disk, executing on a computer. The system balances timing in order to trade off delays between critical and noncritical paths. Register retiming may make changes to a design at a gate level.

公开(公告)号：US08020027B1

公开(公告)日：2011-09-13

申请号：US12049560

申请日：2008-03-17

Applicant: Michael D. Hutton

Inventor： Michael D. Hutton

IPC: G06F1/04 ,  G05F5/06 ,  H03L7/00

CPC classification number: G06F9/3869 ,  H03K19/1774 ,  H03K2005/00058

Abstract: The tension between fmax and Tco in a specialized processing block of a programmable integrated circuit device can be reduced by providing variable delays on the clock inputs of the pipeline registers within the specialized processing block. This allows the introduction of beneficial skew that allows slower functions to be performed within the specialized processing block rather than outside the block, thereby reducing Tco, without slowing down the clock—i.e., without reducing fmax. This technique may also apply to other specialized blocks such as memory.

Abstract translation: 通过在专用处理块内的流水线寄存器的时钟输入端提供可变延迟，可以减少可编程集成电路器件的专用处理块中的fmax和Tco之间的张力。 这允许引入有利的偏移，其允许在专门的处理块内而不是在块之外执行较慢的功能，从而减少Tco，而不会减慢时钟 - 即不降低fmax。 这种技术也可以应用于诸如存储器之类的其他专用块。

公开(公告)号：US07902864B1

公开(公告)日：2011-03-08

申请号：US11292856

申请日：2005-12-01

Applicant: Michael D. Hutton ,  Keith Duwel ,  Gregg William Baeckler

Inventor： Michael D. Hutton ,  Keith Duwel ,  Gregg William Baeckler

IPC: H03K19/177

CPC classification number: H03K19/17736 ,  H03K19/17728

Abstract: Disclosed is a programmable logic device (“PLD”) including at least one lookup table (“LUT”) based logic element (“LE”) of a first type and at least one LUT based LE of a second type. The first type of LE is different from the second type of LE. The term ‘different’ when used herein to describe the relationship of a first logic structure and/or its components to a second logic structure and/or its components indicates a difference in hardware design as opposed to a configuration difference or non-designed differences resulting, for example, from manufacturing variability. Additionally, a PLD can include at least one logic array block (“LAB”) of a first type having at least one LUT based LE and at least one LAB of a second type having at least one LUT based LE. The first type of LAB being different from the second type of LAB.

Abstract translation: 公开了一种包括第一类型的至少一个查找表（“LUT”）逻辑元件（“LE”）和第二类型的至少一个基于LUT的LE的可编程逻辑器件（“PLD”）。 LE的第一种类型与第二种类型的LE不同。 当用于描述第一逻辑结构和/或其组件与第二逻辑结构和/或其组件的关系时，术语“不同”表示硬件设计中的差异，而不是配置差异或非设计的差异 ，例如，从制造变异性。 此外，PLD可以包括具有至少一个基于LUT的LE和具有至少一个基于LUT的LE的至少一个第二类型的至少一个LAB的第一类型的至少一个逻辑阵列块（“LAB”）。 第一种类型的LAB与第二种类型的LAB不同。

公开(公告)号：US20100207659A1

公开(公告)日：2010-08-19

申请号：US12767696

申请日：2010-04-26

Applicant: Michael D. Hutton ,  James G. Schleicher, II ,  Daniel R. Mansur

Inventor： Michael D. Hutton ,  James G. Schleicher, II ,  Daniel R. Mansur

IPC: H03K19/177 ,  G06F17/50

CPC classification number: H03K19/17744 ,  H03K19/17732 ,  H03K19/17796

Abstract: A field programmable gate array (“FPGA”) is provided having integrated application specific integrated circuit (“ASIC”) fabric. The ASIC fabric may be used to implement one or more custom or semi-custom hard blocks within the FPGA. The ASIC fabric can be made up of a “custom region” and an “interface region.” The custom region can implement the custom or semi-custom ASIC design and the interface region can integrate and connect the custom region to the rest of the FPGA circuitry. The custom region may be based on a structured ASIC design. The interface region may allow the ASIC fabric to be incorporated within the hierarchical organization of the FPGA, allowing the custom region to connect to the FPGA circuitry in a seamless manner.

Abstract translation: 提供了具有集成专用集成电路（“ASIC”）结构的现场可编程门阵列（“FPGA”）。 ASIC结构可以用于在FPGA内实现一个或多个定制或半定制硬块。 ASIC结构可以由“自定义区域”和“接口区域”组成。自定义区域可以实现定制或半定制ASIC设计，接口区域可以将自定义区域集成并连接到FPGA的其余部分 电路。 定制区域可以基于结构化ASIC设计。 接口区域可以允许将ASIC结构并入FPGA的分级组织中，从而允许定制区域以无缝的方式连接到FPGA电路。

公开(公告)号：US07607118B1

公开(公告)日：2009-10-20

申请号：US11475843

申请日：2006-06-26

Applicant: Michael D. Hutton

Inventor： Michael D. Hutton

IPC: G06F17/50

CPC classification number: G06F17/5031

Abstract: Techniques are provided for more efficient timing analysis of user designs for programmable ICs. Initially, a graph is created that represents nodes and edges in a user design. Each edge in the graph is assigned a binary edge mask, each bit of which indicates whether it is reachable from a source or destination type relevant to user specified timing constraints. A timing analysis tool then performs multiple depth-first search operations to compute delays along time critical paths relevant to the user specified timing constraints. Because each edge contains an edge mask to indicate whether it connects to a particular source or destination point, the timing analysis tool does not analyze areas of the graph that do not lead to a relevant source or destination point. These techniques prevent the timing analysis tool from analyzing paths in the graph that are not relevant to the analysis of the time critical paths.

Abstract translation: 提供技术用于可编程IC的用户设计的更有效的时序分析。 最初，创建一个表示用户设计中的节点和边的图形。 图中的每个边都被分配一个二进制边缘掩码，其每一位表示是否从与用户指定的时序约束相关的源或目标类型可访问。 定时分析工具然后执行多个深度优先搜索操作，以计算与用户指定的时序约束相关的时间关键路径的延迟。 因为每个边缘都包含一个边缘掩码，以指示它是否连接到特定的源或目标点，所以时序分析工具不分析图形中不会导致相关源或目标点的区域。 这些技术阻止时序分析工具分析图中与时间关键路径分析无关的路径。