公开(公告)号：US12297098B2

公开(公告)日：2025-05-13

申请号：US15824559

申请日：2017-11-28

Applicant: Micron Technology, Inc.

Inventor： Gary L. Howe

IPC: B81B7/00 ,  B81C1/00 ,  G11C11/56

Abstract: A memory device may include a memory array including a plurality of memory cells and a die stack including at least a portion of the plurality of memory cells. The memory device may also include multiple temperature sensors each designed to output a temperature code corresponding to the temperature of a respective die of the die stack. One die of the die stack is then designed to output the temperature code corresponding to the hottest die of the die stack.

公开(公告)号：US20250151276A1

公开(公告)日：2025-05-08

申请号：US19018899

申请日：2025-01-13

Applicant: Micron Technology, Inc.

Inventor： Pei Qiong Cheung ,  Zhixin Xu ,  Yuan Fang

IPC: H10B43/27 ,  H10B43/10

Abstract: Some embodiments include a method of forming an assembly. A first stack of alternating first and second tiers is formed over a conductive structure. A first opening is formed to extend through the first stack. A sidewall of the first opening is lined with a first liner material. The first liner material is converted to a first charge-blocking material. Sacrificial material is formed within the first opening. A second stack of alternating third and fourth tiers is formed over the first stack. A second opening is formed to extend through the second stack to the sacrificial material. A second liner material is formed within the second opening, is anisotropically etched, and is then converted to a second charge-blocking material. The sacrificial material is removed. Charge-storage material, dielectric material and channel material are formed adjacent to the charge-blocking material. Some embodiments include integrated assemblies.

公开(公告)号：US20250149463A1

公开(公告)日：2025-05-08

申请号：US18929394

申请日：2024-10-28

Applicant: Micron Technology, Inc.

Inventor： Po Chien Li ,  Yu Kai Kuo ,  Yi Wen Chen ,  Ming Wei Tsai ,  Chien Nan Fan ,  Chun Ming Huang ,  Angelo Oria Espina ,  Chun Jen Chang

IPC: H01L23/544 ,  H01L21/66 ,  H01L23/00 ,  H01L25/065 ,  H10B80/00

Abstract: Methods, systems, and devices for top die back-side marking for memory systems are described. One or more alignment marks may be added to the back-side of a top memory die in a multi-layer memory device and used to align a position of the top memory die relative to a position of a memory die below the top memory die. The alignment marks may be formed on the top memory die during the manufacturing process of the multi-layer memory device. Operations for forming the alignment marks are described using various semiconductor fabrication techniques. Operations are also disclosed for using the alignment marks to modify placement of the top memory die to reduce the alignment offset in the manufacturing process of subsequent memory dies.

公开(公告)号：US20250149382A1

公开(公告)日：2025-05-08

申请号：US19019070

申请日：2025-01-13

Applicant: Micron Technology, Inc.

Inventor： Kunal R. Parekh

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H10B41/27 ,  H10B43/27

Abstract: A method of forming a microelectronic device comprises forming line structures comprising conductive material and insulative material overlying the conductive material, the line structures separated from one another by trenches. An isolation material is formed on surfaces of the line structures inside and outside of the trenches, the isolation material only partially filling the trenches to form air gaps interposed between the line structures. Openings are formed to extend through the isolation material and expose portions of the insulative material of the line structures. The exposed portions of the insulative material of the line structures are removed to form extended openings extending to the conductive material of the line structures. Conductive contact structures are formed within the extended openings. Conductive pad structures are formed on the conductive contact structures. Additional methods, microelectronic devices, memory devices, and electronic systems are also described.

公开(公告)号：US20250149094A1

公开(公告)日：2025-05-08

申请号：US19008495

申请日：2025-01-02

Applicant: Micron Technology, Inc.

Inventor： Vinh Q. Diep ,  Yingda Dong ,  Ching-Huang Lu

IPC: G11C16/12 ,  G11C16/08 ,  G11C16/28 ,  G11C16/30

Abstract: Control logic can perform operations including obtaining, for each dummy wordline of a set of dummy wordlines, a respective set of step-up voltage parameters, wherein each set of step-up voltage parameters includes a step ratio corresponding to the dummy wordline, and causing a bias voltage with respect to each dummy wordline of the set of dummy wordlines to be ramped to a respective program inhibit bias voltage in accordance with the respective set of step-up voltage parameters. Additionally or alternatively, control logic can perform memory operations including causing a bias voltage with respect to each dummy wordline to be ramped to a power supply voltage during a seed first sub-phase of a pre-programming phase, and maintaining the bias voltage of the first dummy wordline at a first dummy wordline seed voltage throughout a bitline setting sub-phase of the pre-programming phase.

公开(公告)号：US20250149072A1

公开(公告)日：2025-05-08

申请号：US19013290

申请日：2025-01-08

Applicant: Micron Technology, Inc.

Inventor： Ugo Russo

IPC: G11C7/10 ,  G11C8/12 ,  G11C11/56 ,  G11C16/08 ,  G11C19/32 ,  H10B41/35 ,  H10B43/27

Abstract: Some embodiments include an assembly having a stack of alternating dielectric levels and conductive levels. Channel material pillars extend through the stack. Some of the channel material pillars are associated with a first sub-block, and others of the channel material pillars are associated with a second sub-block. Memory cells are along the channel material pillars. An insulative level is over the stack. A select gate configuration is over the insulative level. The select gate configuration includes a first conductive gate structure associated with the first sub-block, and includes a second conductive gate structure associated with the second sub-block. The first and second conductive gate structures are laterally spaced from one another by an intervening insulative region. The first and second conductive gate structures have vertically-spaced conductive regions, and have vertically-extending conductive structures which electrically couple the vertically-spaced conductive regions to one another. Some embodiments include methods of forming assemblies.

公开(公告)号：US20250148275A1

公开(公告)日：2025-05-08

申请号：US19018884

申请日：2025-01-13

Applicant: Micron Technology, Inc.

Inventor： Poorna Kale

IPC: G06N3/063 ,  G06F9/30 ,  G06F9/50 ,  G06F17/16 ,  G06F30/27 ,  G06N3/08

Abstract: Systems, devices, and methods related to a deep learning accelerator and memory are described. For example, an integrated circuit device may be configured to execute instructions with matrix operands and configured with random access memory (RAM) to store parameters of an artificial neural network (ANN). The device can generate random bit errors to simulate compromised or corrupted memory cells in a portion of the RAM accessed during computations of a first ANN output. A second ANN output is generated with the random bit errors applied to the data retrieved from the portion of the RAM. Based on a difference between the first and second ANN outputs, the device may adjust the ANN computation to reduce sensitivity to compromised or corrupted memory cells in the portion of the RAM. For example, the sensitivity reduction may be performed through ANN training using machine learning.

公开(公告)号：US20250147897A1

公开(公告)日：2025-05-08

申请号：US19017035

申请日：2025-01-10

Applicant: Micron Technology, Inc.

Inventor： Dmitri Yudanov ,  Ameen D. Akel ,  Samuel E. Bradshaw ,  Kenneth Marion Curewitz ,  Sean Stephen Eilert

IPC: G06F12/1009 ,  G06F12/1027 ,  G06N5/043 ,  G06N5/045 ,  H04L67/1097 ,  H04L67/568 ,  H04W8/26

Abstract: Systems, methods and apparatuses of fine grain data migration in using memory as a service (MaaS) are described. For example, a memory status map can be used to identify the cache availability of sub-regions (e.g., cache lines) of a borrowed memory region (e.g., a borrowed remote memory page). Before accessing a virtual memory address in a sub-region, the memory status map is checked. If the sub-region has cache availability in the local memory, the memory management unit uses a physical memory address converted from the virtual memory address to make memory access. Otherwise, the sub-region is cached from the borrowed memory region to the local memory, before the physical memory address is used.

公开(公告)号：US20250147846A1

公开(公告)日：2025-05-08

申请号：US18776211

申请日：2024-07-17

Applicant: Micron Technology, Inc.

Inventor： Marco Redaelli ,  Gaurav Sinha ,  Zhang Lei

IPC: G06F11/10 ,  G06F11/07

Abstract: Methods, systems, and devices for sorting retired blocks of non-volatile memory cells are described. A memory system may recover a block that has been marked as “bad” using a requalification process. For example, after operating in an error protection mode for the block, the memory system may monitor the block to determine whether a status flag indicating an access error is set. If the status flag is set, the memory system may store information that indicates the block is unrecoverable, and the block may subsequently be retired. Alternatively, if a status flag is not set, the memory system may store information that indicates the block may be recoverable. If one or more additional access operations to the block are successful, the memory system may store information that indicates the block may be used for subsequent access operations.

公开(公告)号：US20250147843A1

公开(公告)日：2025-05-08

申请号：US18777165

申请日：2024-07-18

Applicant: Micron Technology, Inc.

Inventor： Shivasankar Gunasekaran ,  Sai Krishna Mylavarapu

IPC: G06F11/10

Abstract: Methods, systems, and devices for data routing for error correction in stacked memory architectures are described. A system may support error correction of bits of data communicated between a first semiconductor die (e.g., an array die) and a second semiconductor die (e.g., a logic die). For example, an interface of the second semiconductor die may receive data stored at a memory array of the first semiconductor die. The interface may include error correction engines each operable to correct one or more bit errors. The interface may also include logic circuitry operable to route physically-grouped subsets of the received data to respective error correction engines, and such subsets may be configured to allocate the error correction engines in manner that improves a likelihood that physically-grouped errors in the system can be corrected. The interface may output the data to a host system after the error control operations are performed.