公开(公告)号：US08803241B2

公开(公告)日：2014-08-12

申请号：US13538734

申请日：2012-06-29

Applicant: Jr-Jung Lin ,  Chih-Han Lin ,  Ming-Ching Chang

Inventor： Jr-Jung Lin ,  Chih-Han Lin ,  Ming-Ching Chang

IPC: H01L21/70

CPC classification number: H01L29/66795 ,  H01L21/30604 ,  H01L21/823431 ,  H01L29/42372 ,  H01L29/66545 ,  H01L29/6681

Abstract: The disclosure relates to a dummy gate electrode of a semiconductor device. An embodiment comprises a substrate comprising a first surface; an insulation region covering a portion of the first surface, wherein the top of the insulation region defines a second surface; and a dummy gate electrode over the second surface, wherein the dummy gate electrode comprises a bottom and a base broader than the bottom, wherein a ratio of a width of the bottom to a width of the base is from about 0.5 to about 0.9.

Abstract translation: 本公开涉及半导体器件的虚拟栅电极。 一个实施例包括一个包括第一表面的基底; 覆盖所述第一表面的一部分的绝缘区域，其中所述绝缘区域的顶部限定第二表面; 以及在所述第二表面上的虚拟栅电极，其中所述虚拟栅电极包括底部和比所述底部宽的底部，其中所述底部的宽度与所述基部的宽度的比率为约0.5至约0.9。

公开(公告)号：US08691655B2

公开(公告)日：2014-04-08

申请号：US13471649

申请日：2012-05-15

Applicant: Tzu-Yen Hsieh ,  Ming-Ching Chang ,  Yuan-Sheng Huang ,  Ming-Chia Tai ,  Chao-Cheng Chen

Inventor： Tzu-Yen Hsieh ,  Ming-Ching Chang ,  Yuan-Sheng Huang ,  Ming-Chia Tai ,  Chao-Cheng Chen

IPC: H01L21/02

CPC classification number: H01L27/0629 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of fabricating a semiconductor integrated circuit (IC) is disclosed. The method includes receiving a semiconductor device, patterning a first hard mask to form a first recess in a high-resistor (Hi-R) stack, removing the first hard mask, forming a second recess in the Hi-R stack, forming a second hard mask in the second recess in the Hi-R stack. A HR can then be formed in the semiconductor substrate by the second hard mask and a gate trench etch.

Abstract translation: 公开了制造半导体集成电路（IC）的方法。 该方法包括接收半导体器件，图案化第一硬掩模以在高电阻（Hi-R）堆叠中形成第一凹槽，去除第一硬掩模，在Hi-R堆叠中形成第二凹槽，形成第二 硬掩模在Hi-R堆叠的第二个凹槽中。 然后可以通过第二硬掩模和栅沟​​槽蚀刻在半导体衬底中形成HR。

公开(公告)号：US20130138505A1

公开(公告)日：2013-05-30

申请号：US13308376

申请日：2011-11-30

Applicant: Peter Henry Tu ,  Mark Lewis Grabb ,  Xiaoming Liu ,  Ting Yu ,  Yi Yao ,  Dashan Gao ,  Ming-Ching Chang

Inventor： Peter Henry Tu ,  Mark Lewis Grabb ,  Xiaoming Liu ,  Ting Yu ,  Yi Yao ,  Dashan Gao ,  Ming-Ching Chang

IPC: G06Q30/02

CPC classification number: G06Q30/02

Abstract: An advertising system is disclosed. In one embodiment, the system includes a processor and a memory including application instructions for execution by the processor. The application instructions may include a visual analytics engine to analyze visual information including human activity and a content engine separate from the visual analytics engine to provide advertising content to one or more potential customers. Further, the instructions may include an interface module to enable information generated from analysis of the human activity by the visual analytics engine to be transferred to the content engine in accordance with a specification in which the information generated is characterized with a hierarchical, object-oriented data structure. Additional methods, systems, and articles of manufacture are also disclosed.

Abstract translation: 公开了广告系统。 在一个实施例中，该系统包括处理器和包括由处理器执行的应用指令的存储器。 应用指令可以包括视觉分析引擎，用于分析包括人类活动的视觉信息和与视觉分析引擎分离的内容引擎，以向一个或多个潜在客户提供广告内容。 此外，指令可以包括接口模块，用于根据其中所生成的信息以层次化，面向对象的特征来指示由视觉分析引擎分析人类活动而产生的信息被传送到内容引擎 数据结构。 还公开了附加的方法，系统和制品。

公开(公告)号：US20120095582A1

公开(公告)日：2012-04-19

申请号：US12905354

申请日：2010-10-15

Applicant: Bing-Hung Chen ,  Ming-Ching Chang

Inventor： Bing-Hung Chen ,  Ming-Ching Chang

IPC: G05B13/04 ,  G05B13/02

CPC classification number: G06Q10/06 ,  G05B13/024 ,  G05B13/042 ,  G05B19/41875 ,  G05B2219/45031

Abstract: The present disclosure provides a method of chamber match. The method includes identifying a golden chamber designed operable to implement a semiconductor process; identifying a reference chamber designed operable for the semiconductor process; and extracting a matching index of a processing chamber relative to the golden chamber and the reference chamber using a dynamic variable analysis.

Abstract translation: 本公开提供了室匹配的方法。 该方法包括识别可操作以实现半导体工艺的金室; 识别设计用于半导体工艺的参考室; 以及使用动态变量分析提取处理室相对于黄金室和参考室的匹配指数。

公开(公告)号：US20050106888A1

公开(公告)日：2005-05-19

申请号：US10714207

申请日：2003-11-14

Applicant: Yuan-Hung Chiu ,  Ming-Ching Chang ,  Hun-Jan Tao

Inventor： Yuan-Hung Chiu ,  Ming-Ching Chang ,  Hun-Jan Tao

IPC: G03F7/42 ,  H01L21/302 ,  H01L21/306 ,  H01L21/311 ,  H01L21/461 ,  H01L21/768

CPC classification number: H01L21/31116 ,  G03F7/427 ,  H01L21/02046 ,  H01L21/02063 ,  H01L21/31138 ,  H01L21/76802 ,  H01L21/76814

Abstract: An integrated process flow including a plasma step for removing oxide residues following oxygen ashing of a photoresist layer is disclosed. The oxide removal step is effective in preventing micro mask defects and is preferably performed in the same process chamber used for the oxygen ashing step and for a subsequent plasma etch used for pattern transfer. The oxide removal step takes less than 60 seconds and involves a halogen containing plasma that is generated from one or more of NF3, Cl2, CF4, CH2F2, and SF6. Optionally, HBr or a fluorocarbon CXFYHZ where x and y are integers and z is an integer or is equal to 0 may be used alone or with one of the aforementioned halogen containing gases. The oxide removal step may be incorporated in a variety of applications including a damascene scheme, shallow trench (STI) fabrication, or formation of a gate electrode in a transistor.

Abstract translation: 公开了一种集成工艺流程，其包括用于除去光致抗蚀剂层的氧灰化之后的氧化物残余物的等离子体步骤。 氧化物去除步骤在防止微掩模缺陷方面是有效的，并且优选在用于氧灰化步骤的相同处理室和用于图案转移的后续等离子体蚀刻中进行。 氧化物去除步骤需要少于60秒，并且涉及从NF 3，Cl 2，CF 4，...中的一个或多个产生的含卤素等离子体， SUB 2，CH 2，2 F 2和SF 6。 可选地，HBr或碳氟化合物其中x和y是整数，z是整数或等于0可以是 可以单独使用或与上述含卤素气体中的一种一起使用。 氧化物去除步骤可以结合在各种应用中，包括镶嵌方案，浅沟槽（STI）制造或在晶体管中形成栅电极。

公开(公告)号：US06864174B2

公开(公告)日：2005-03-08

申请号：US10394334

申请日：2003-03-20

Applicant: Li-Te S. Lin ,  Yui Wang ,  Ming-Ching Chang ,  Li-Shung Chen ,  Huain-Jelin Lin ,  Yuan-Hong Chin ,  Hong-Yuan Tao

Inventor： Li-Te S. Lin ,  Yui Wang ,  Ming-Ching Chang ,  Li-Shung Chen ,  Huain-Jelin Lin ,  Yuan-Hong Chin ,  Hong-Yuan Tao

IPC: H01L21/00 ,  H01L21/66 ,  H01L21/302

CPC classification number: H01L21/67253 ,  H01J37/32935 ,  H01L21/67069 ,  H01L22/00

Abstract: A method for compensating for CD variations across a semiconductor process wafer surface in a plasma etching process including providing a semiconductor wafer having a process surface including photolithographically developed features imaged from a photomask; determining a first dimensional variation of the features with respect to corresponding photomask dimensions along at least one wafer surface direction to determine a first levelness of the process surface; determining gas flow parameters in a plasma reactor for a plasma etching process required to approach a level process surface by reference to an archive of previous plasma etching process parameters carried out in the plasma reactor; carrying out the plasma etching process in the plasma rector according to the determined gas flow parameters; and, determining a second dimensional variation of the features along the at least one wafer surface direction to determine a second levelness of the process surface.

Abstract translation: 一种用于补偿等离子体蚀刻工艺中的半导体工艺晶片表面上的CD变化的方法，包括提供具有包括从光掩模成像的光刻显影特征的工艺表面的半导体晶片; 沿着至少一个晶片表面方向确定相对于相应光掩模尺寸的特征的第一尺寸变化，以确定所述工艺表面的第一平坦度; 确定等离子体反应器中的气体流量参数，用于通过参考在等离子体反应器中进行的先前等离子体蚀刻工艺参数的归档来等离子体蚀刻工艺所需的接近水平工艺表面; 根据确定的气体流量参数在等离子体检测器中进行等离子体蚀刻工艺; 以及确定所述特征沿所述至少一个晶片表面方向的第二维度变化以确定所述过程表面的第二平坦度。