公开(公告)号：US06781410B2

公开(公告)日：2004-08-24

申请号：US10412975

申请日：2003-04-11

申请人： Peter M. Pani ,  Benjamin S. Ting

发明人： Peter M. Pani ,  Benjamin S. Ting

IPC分类号： H03K19177

CPC分类号： H03K19/17704 ,  H03K19/17728 ,  H03K19/17732 ,  H03K19/17736 ,  H03K19/1776 ,  H03K19/1778 ,  H03K19/17796

摘要： The system and method of the present invention provides an innovative bus system of lines which can be programmed and to provide data, control and address information to the logic circuits interconnected by the bus system. This flexible structure and process enables a configurable system to be created to programmably connect one or more logic circuits, such as megacells. The programmability of the bus system enables the cascading of multiple megacells in an arbitrary fashion (i.e., wide, deep or both) and the sharing of common lines for system level communication.

摘要翻译： 本发明的系统和方法提供了一种创新的线路总线系统，其可以被编程并且向由总线系统互连的逻辑电路提供数据，控制和地址信息。 这种灵活的结构和过程使得能够创建可配置系统以可编程地连接一个或多个逻辑电路，例如兆位。 总线系统的可编程性使得能够以任意方式（即，宽，深或两者）级联多个兆位，并且共享用于系统级通信的公共线。

公开(公告)号：US06417690B1

公开(公告)日：2002-07-09

申请号：US09089298

申请日：1998-06-01

申请人： Benjamin S. Ting ,  Peter M. Pani

发明人： Benjamin S. Ting ,  Peter M. Pani

IPC分类号： G06F900

CPC分类号： H03K19/17736 ,  H03K19/17704 ,  H03K19/17792 ,  H03K19/17796

摘要： A programmable logic device which incorporates an innovative routing hierarchy consisting of the multiple levels of routing lines, connector tab networks and turn matrices, enables an innovative, space saving floor plan to be utilized in an integrated circuit implementation, and is particularly efficient when an SRAM is used as the configuration bit. This floor plan is a scalable block architecture in which each block connector tab networks of a 2×2 block grouping is arranged as a mirror image along the adjacent axis relative to each other. Furthermore, the bidirectional input/output lines are provided as the input/output means for each block are oriented only in two directions such that the block connector tab networks for adjacent blocks face each other in orientation. This orientation and arrangement permits blocks to share routing resources. In addition, this arrangement permits blocks to share routing resources. In addition, this arrangement enables a 4×4 block grouping to be scalable. The innovative floor plan makes efficient use of die space with little layout dead space as the floor plan provides for a plurality of contiguous memory and passgate arrays (which provide functionality of the bidirectional switches) with small regions of logic for CFGs and drivers of the block connector tab networks. Therefore, the gaps typically incurred due to a mixture of memory and logic are avoided. Intra-cluster routing lines and bi-directional routing lines are overlayed on different layers of the chip together with memory and passgate arrays to provide connections to higher level routing lines and connections between CFGs in the block.

摘要翻译： 一种可编程逻辑器件，其结合了由多层次的布线线，连接器标签网络和转向矩阵组成的创新路由层次结构，能够在集成电路实现中使用创新的节省空间的平面图，并且当SRAM 用作配置位。 该平面图是可扩展的块结构，其中将2x2块分组的每个块连接器选项卡网络相对于彼此沿着相邻的轴线布置为镜像。 此外，双向输入/输出线被提供，因为每个块的输入/输出装置仅在两个方向上取向，使得相邻块的块连接器选项卡网络在取向上彼此面对。 这种方向和布置允许块共享路由资源。 此外，这种布置允许块共享路由资源。 此外，这种布置使得4×4块分组能够可扩展。 创新的平面图使得有效地利用具有很小的布局死空间的管芯空间，因为平面图为多个连续的存储器和通道阵列（其提供双向开关的功能）提供了用于CFG和块的驱动器的小的逻辑区域 连接器标签网络。 因此，避免了由于存储器和逻辑的混合引起的间隙。 集群内路由线路和双向路由线路与芯片的不同层与存储器和传递门阵列重叠，以提供与较高级路由线路的连接以及块中CFG之间的连接。

公开(公告)号：US06320412B1

公开(公告)日：2001-11-20

申请号：US09467736

申请日：1999-12-20

申请人： Benjamin S. Ting ,  Peter M. Pani

发明人： Benjamin S. Ting ,  Peter M. Pani

IPC分类号： H03K19177

CPC分类号： H03K19/17736

摘要： An improved programmable logic device and interconnect architecture is provided. In one embodiment an interconnect network provides programmable routing between calls. In one embodiment the interconnect network includes first routing lines of a first level of routing lines, second routing lines of a second level of routing lines and third routing lines of a third level of routing lines. The first and second routing lines are programmably and bidirectionally coupled to the third routing lines such that signals are selectively driven from either the first or second routing lines to the third routing lines and signals are selectively driven from the third routing lines to the first routing lines and second routing lines.

摘要翻译： 提供了一种改进的可编程逻辑器件和互连架构。 在一个实施例中，互连网络在呼叫之间提供可编程路由。 在一个实施例中，互连网络包括第一级路由线路的第一路由线路，第二级路由线路的第二路由线路和第三级路由线路的第三路由线路。 第一和第二路由线可编程地和双向地耦合到第三路由线，使得信号被选择性地从第一或第二路由线路驱动到第三路由线路，并且信号被选择性地从第三路由线路驱动到第一路由线路 和第二路由线路。

公开(公告)号：US6034547A

公开(公告)日：2000-03-07

申请号：US708403

申请日：1996-09-04

申请人： Peter M. Pani ,  Benjamin S. Ting

发明人： Peter M. Pani ,  Benjamin S. Ting

IPC分类号： G06F13/36 ,  H03K19/173 ,  H03K19/177

CPC分类号： H03K19/17736 ,  H03K19/17704 ,  H03K19/17728 ,  H03K19/17744 ,  H03K19/17796

摘要： The system and method of the present invention provides an innovative bus system of lines which can be programmed and to provide data, control and address information to the logic circuits interconnected by the bus system. This flexible structure and process enables a configurable system to be created to programmably connect one or more logic circuits, such as megacells. The programmability of the bus system enables the cascading of multiple megacells in an arbitrary fashion (i.e., wide, deep or both) and the sharing of common lines for system level communication.

摘要翻译： 本发明的系统和方法提供了一种创新的线路总线系统，其可以被编程并且向由总线系统互连的逻辑电路提供数据，控制和地址信息。 这种灵活的结构和过程使得能够创建可配置系统以可编程地连接一个或多个逻辑电路，例如兆位。 总线系统的可编程性使得能够以任意方式（即，宽，深或两者）级联多个兆位，并且共享用于系统级通信的公共线。

公开(公告)号：US5640344A

公开(公告)日：1997-06-17

申请号：US506828

申请日：1995-07-25

申请人： Peter M. Pani ,  Benjamin S. Ting ,  Benny Ma

发明人： Peter M. Pani ,  Benjamin S. Ting ,  Benny Ma

IPC分类号： G11C16/04 ,  H01L21/82 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H03K17/687 ,  H03K17/693 ,  G11C11/40

CPC分类号： H03K17/693 ,  G11C16/0441 ,  H03K17/687

摘要： A bidirectional passgate switch for connecting two conductors utilizes technology such as electrically erasable programmable read only memory (EEPROM). The switch includes two EEPROM components wherein the floating gates of the components are shared. In one embodiment a first n-channel passgate transistor is used for programming and storage of the state of the switch. The oxide of the first transistor is a thin oxide to enable ease of programming. A second n-channel passgate transistor functions as the bidirectional switch wherein the source and drain terminals are coupled to the routing lines to be selectively connected. The second transistor oxide is a thick oxide to minimize the leakage due to tunneling. Thus, the programming lines and routing lines are separated, making the programming process simpler while minimizing leakage.

摘要翻译： 用于连接两个导体的双向通道开关利用诸如电可擦除可编程只读存储器（EEPROM）的技术。 该开关包括两个EEPROM组件，其中组件的浮动栅极被共享。 在一个实施例中，第一n沟道通道晶体管用于编程和存储开关的状态。 第一晶体管的氧化物是薄氧化物，以便于编程。 第二n沟道通道晶体管用作双向开关，其中源极和漏极端子耦合到路由线以被选择性地连接。 第二晶体管氧化物是厚氧化物，以使由隧道引起的泄漏最小化。 因此，编程线和路由线分开，使编程过程更简单，同时最小化泄漏。

公开(公告)号：US08698519B2

公开(公告)日：2014-04-15

申请号：US13551011

申请日：2012-07-17

申请人： Peter M. Pani ,  Benjamin S. Ting

发明人： Peter M. Pani ,  Benjamin S. Ting

IPC分类号： H03K19/177 ,  H01L21/82

CPC分类号： H03K19/17736 ,  H03K17/002 ,  H04L49/15 ,  H04L49/1515 ,  Y10T29/49002 ,  Y10T29/49117

摘要： A L-level permutable switching network (L-PSN) having switches and multiple levels of conductors that are used to connect a first plurality of conductors to other multiple sets of conductors within respective interconnect resources constraints. The L-PSN can be applied in a wide range of applications, in tandem or hierarchically, to provide a large switch network used in network, routers, and programmable logic circuits. The L-PSN is used to connect a first set of conductors, through the L-PSN, to multiple sets of conductors in a given logic circuit hierarchy whereby the conductors in each of the multiple sets are equivalent or exchangeable, which in term, by construction, makes the first set of conductors equivalent when used in the next level of circuit hierarchy. The L-PSN is scalable for large sized sets of conductors and can be used in tandem or hierarchically to enable programmable interconnections among large sized circuits.

摘要翻译： 具有开关和多级导体的L级置换开关网络（L-PSN），其用于将第一多个导体连接到相应互连资源约束内的其它多组导体。 L-PSN可以串联或分层应用于广泛的应用，以提供在网络，路由器和可编程逻辑电路中使用的大型交换机网络。 L-PSN用于通过L-PSN将第一组导体连接到给定逻辑电路层级中的多组导体，从而多组中的每一个中的导体是等价的或可交换的，其中，通过 构造时，使第一组导体在下一级电路层级使用时相当。 L-PSN可针对大尺寸导体进行扩展，可以串联或分级使用，以实现大尺寸电路之间的可编程互连。

公开(公告)号：US20110267104A1

公开(公告)日：2011-11-03

申请号：US13179342

申请日：2011-07-08

申请人： Benjamin S. Ting ,  Peter M. Pani

发明人： Benjamin S. Ting ,  Peter M. Pani

IPC分类号： H03K19/177 ,  H01L21/82

CPC分类号： H03K19/17736 ,  H04L49/10

摘要： An integrated circuit having an L-level permutable switching network (L-PSN) comprising L levels of intermediate conductors and (L+2) levels of conductors for L at least equal to one. At least an (i−1)-th level of conductors of the L-PSN comprising Li−1 number of conductors selectively couple to the i-th level of conductors comprising Ii number of conductors which comprise of D[i] sets of conductors in the L-PSN, where i is selected from [1:L+1], through ((Ii−1×D[i])+Ii) number of switches where each conductor of the Li−1 number of conductors selectively couples to at least (D[i]+1) number of conductors of the Ii number of conductors, at least one conductor from each of the D[i] sets of conductors, for D[i] greater than one. The integrated circuit can be used in various electronic devices.

摘要翻译： 一种集成电路，其具有包括L级中间导体和L（L + 2）级导体的L级置换开关网络（L-PSN），L级至少等于1。 包含Li-1数量的导体的L-PSN的导体的至少第（i-1）个级别选择性地耦合到包括由D [i]组导体组成的I i个导体数量的第i级导体 在L-PSN中，其中i选自[1：L + 1]，到（（Ii-1×D [i]）+ Ii）个开关，其中Li-1数量的导体选择性耦合 至少（D [i] +1）个导体数量的导体，D [i]组导体中的至少一个导体，D [i]大于1的导体。 集成电路可用于各种电子设备。

公开(公告)号：US07986163B2

公开(公告)日：2011-07-26

申请号：US12955738

申请日：2010-11-29

申请人： Peter M. Pani ,  Benjamin S. Ting

发明人： Peter M. Pani ,  Benjamin S. Ting

IPC分类号： H03K19/177 ,  H01L21/82

CPC分类号： H03K19/17736 ,  H03K17/002 ,  H04L49/15 ,  H04L49/1515 ,  Y10T29/49002 ,  Y10T29/49117

摘要： A scalable non-blocking switching network (SN) having switches and intermediate (stages of) conductors that are used to connect a first plurality of conductors to other multiple sets of conductors in a generally unrestricted fashion within respective interconnect resources constraints. The SN can be applied in a wide range of applications, in tandem or hierarchically, to provide a large switch network used in network, routers, and programmable logic circuits. The SN is used to connect a first set of conductors, through the SN, to multiple sets of conductors in a given logic circuit hierarchy whereby the conductors in each of the multiple sets are equivalent or exchangeable, which in term, by construction, makes the first set of conductors equivalent when used in the next level of circuit hierarchy. The SN is scalable for large sized sets of conductors and can be used hierarchically to enable programmable interconnections among large sized circuits.

摘要翻译： 具有开关和中间（级）导体的可扩展的非阻塞交换网络（SN），其用于在相应的互连资源约束内以大致无限制的方式将第一多个导体连接到其它多组导体。 SN可以应用在广泛的应用中，一起或分层，以提供在网络，路由器和可编程逻辑电路中使用的大型交换机网络。 SN用于将第一组导体（通过SN）连接到给定逻辑电路层级中的多组导体，由此多个组中的每一个中的导体是等同的或可交换的，其在结构上使得 当用于下一级电路层级时，第一组导体相当。 SN可针对大型导体组进行扩展，可以分级使用，以实现大尺寸电路之间的可编程互连。

公开(公告)号：US20100141298A1

公开(公告)日：2010-06-10

申请号：US12703624

申请日：2010-02-10

申请人： Peter M. Pani ,  Benjamin S. Ting

发明人： Peter M. Pani ,  Benjamin S. Ting

IPC分类号： H03K19/177 ,  H05K3/00

CPC分类号： H03K19/17704 ,  H03K19/17736 ,  Y10T29/49124 ,  Y10T29/49128 ,  Y10T29/49155

摘要： In one embodiment, an integrated circuit has a L-level permutable switching network (L-PSN) comprising L levels of intermediate conductors. The integrated circuit can be used in electronic devices, such as switching networks, routers, and programmable logic circuits, etc.

公开(公告)号：US20090273368A1

公开(公告)日：2009-11-05

申请号：US12472305

申请日：2009-05-26

申请人： Peter M. Pani ,  Benjamin S. Ting

发明人： Peter M. Pani ,  Benjamin S. Ting

IPC分类号： H03K19/177 ,  H01S4/00

CPC分类号： H03K19/17736 ,  H03K17/002 ,  H04L49/15 ,  H04L49/1515 ,  Y10T29/49002 ,  Y10T29/49117

摘要： A scalable non-blocking switching network (SN) having switches and intermediate (stages of) conductors that are used to connect a first plurality of conductors to other multiple sets of conductors in a generally unrestricted fashion within respective interconnect resources constraints. The SN can be applied in a wide range of applications, in tandem or hierarchically, to provide a large switch network used in network, routers, and programmable logic circuits. The SN is used to connect a first set of conductors, through the SN, to multiple sets of conductors in a given logic circuit hierarchy whereby the conductors in each of the multiple sets are equivalent or exchangeable, which in term, by construction, makes the first set of conductors equivalent when used in the next level of circuit hierarchy. The SN is scalable for large sized sets of conductors and can be used hierarchically to enable programmable interconnections among large sized circuits.

摘要翻译： 具有开关和中间（级）导体的可扩展的非阻塞交换网络（SN），其用于在相应的互连资源约束内以大致无限制的方式将第一多个导体连接到其它多组导体。 SN可以应用在广泛的应用中，一起或分层，以提供在网络，路由器和可编程逻辑电路中使用的大型交换机网络。 SN用于将第一组导体（通过SN）连接到给定逻辑电路层级中的多组导体，由此多个组中的每一个中的导体是等同的或可交换的，其在结构上使得 当用于下一级电路层级时，第一组导体相当。 SN可针对大型导体组进行扩展，可以分级使用，以实现大尺寸电路之间的可编程互连。