公开(公告)号：US07043405B2

公开(公告)日：2006-05-09

申请号：US10964413

申请日：2004-10-12

申请人： Doron Orenstien ,  Ronny Ronen

发明人： Doron Orenstien ,  Ronny Ronen

IPC分类号： G06F13/00

CPC分类号： G06F9/4856 ,  G06F1/206 ,  G06F1/3203 ,  G06F1/324 ,  G06F1/3243 ,  G06F1/3287 ,  G06F1/329 ,  G06F1/3296 ,  G06F9/5094 ,  Y02D10/126 ,  Y02D10/152 ,  Y02D10/16 ,  Y02D10/171 ,  Y02D10/172 ,  Y02D10/22 ,  Y02D10/24 ,  Y02D10/32 ,  Y02D50/20

摘要： Distribution of processing activity across processing hardware based on power consumption and/or thermal considerations. One embodiment includes a plurality of processing units and a monitor to obtain monitor (e.g., power consumption, or temperature or some combination thereof) values from the processing units. The monitor transfers a process from one processing unit to another in response to the monitor values from the processing units.

摘要翻译： 基于功耗和/或热考虑分布处理硬件的处理活动。 一个实施例包括多个处理单元和监视器以从处理单元获得监视器（例如，功率消耗，或其温度或其组合）值。 响应于来自处理单元的监视值，监视器将处理从一个处理单元传送到另一处理单元。

公开(公告)号：US06742112B1

公开(公告)日：2004-05-25

申请号：US09473976

申请日：1999-12-29

申请人： Adi Yoaz ,  Ronny Ronen ,  Stephan J. Jourdan ,  Michael Bekerman

发明人： Adi Yoaz ,  Ronny Ronen ,  Stephan J. Jourdan ,  Michael Bekerman

IPC分类号： G06F934

CPC分类号： G06F9/30134 ,  G06F9/30167 ,  G06F9/383 ,  G06F9/3832 ,  G06F9/3842

摘要： Apparatus and methods to track a register value. A microprocessor can include a first register, a control circuit, and an adder. The first register can store a tracked register value. The control circuit can include an instruction input to receive at least a portion of an instruction and a first output to output an arithmetic operation indication. The adder can include a control input to receive the arithmetic operation indication, a first input to receive an immediate operand of an instruction, and a second input to receive the tracked register value.

摘要翻译： 跟踪寄存器值的装置和方法。 微处理器可以包括第一寄存器，控制电路和加法器。 第一个寄存器可以存储跟踪的寄存器值。 控制电路可以包括用于接收指令的至少一部分的指令输入和用于输出算术运算指示的第一输出。 加法器可以包括用于接收算术运算指示的控制输入，用于接收指令的立即操作数的第一输入和用于接收所跟踪的寄存器值的第二输入。

公开(公告)号：US06697932B1

公开(公告)日：2004-02-24

申请号：US09475645

申请日：1999-12-30

申请人： Adi Yoaz ,  Mattan Erez ,  Ronny Ronen

发明人： Adi Yoaz ,  Mattan Erez ,  Ronny Ronen

IPC分类号： G06F938

CPC分类号： G06F9/3838 ,  G06F9/3824 ,  G06F9/3836 ,  G06F9/3844 ,  G06F9/3857 ,  G06F9/3861

摘要： The present invention is directed to a computer system and method for early resolution of a set of critical instructions. The computer system may include a scoreboard, a scheduling window and a confidence predictor. The scoreboard may include a set of reservation stations. Each one of the set of reservation stations may correspond to one of a set of decoded instructions. Each one of the set of reservation stations may have a priority field. The scheduling window may maintain the scoreboard, wherein if one of the set of decoded instructions is one of the set of critical instructions, the scheduling window may mark the priority field corresponding to the particular one of the set of decoded instructions and also may find and mark the priority field of each of a set of base instructions upon which the particular one of the set of decoded instructions depends. The confidence predictor may also be used to predict whether one of the set of decoded instructions is one of the set of critical instructions.

摘要翻译： 本发明涉及一种用于早期解决一组关键指令的计算机系统和方法。 计算机系统可以包括记分板，调度窗口和置信度预测器。 记分板可以包括一组保留站。 该组保留站中的每一个可对应于一组解码指令中的一个。 该组保留站中的每一个可以具有优先级字段。 调度窗口可以维持记分板，其中如果解码指令集合中的一个是关键指令集合中的一个，则调度窗口可以标记与该组解码指令中的特定一个对应的优先级字段，并且还可以找到和 标记所述一组解码指令中的特定一个所依赖的一组基本指令中的每一个的优先级字段。 置信度预测器还可以用于预测该组解码指令中的一个是否是该组关键指令之一。

公开(公告)号：US06647482B1

公开(公告)日：2003-11-11

申请号：US09545056

申请日：2000-04-07

申请人： Ronny Ronen ,  Andrew F. Glew ,  Maury J. Bach ,  Robert C. Valentine ,  Richard A. Uhlig ,  Opher D. Kahn

发明人： Ronny Ronen ,  Andrew F. Glew ,  Maury J. Bach ,  Robert C. Valentine ,  Richard A. Uhlig ,  Opher D. Kahn

IPC分类号： G06F1204

CPC分类号： G06F12/1009 ,  G06F2212/652

摘要： Method for producing a predetermined length page memory pointer record, according to a selected page size and a selected page address, the method including the procedures of: determining a dynamic location of a separator bit within the page memory pointer record, according to the selected page size and an initial page size, the initial page size being respective of the smallest page size in a given memory system, writing a predetermined value to the dynamic location, writing a sequence of values opposite to the predetermined value to selected page size bits of the page memory pointer record, when the selected page size is different than the initial page size, and writing the selected page address to selected page address bits of the page memory pointer record.

摘要翻译： 根据所选择的页面大小和所选择的页面地址来生成预定长度的页面存储器指针记录的方法，所述方法包括以下过程：根据所选择的页面确定页面存储器指针记录中的分隔符位置的动态位置 大小和初始页面大小，初始页面大小相应于给定存储器系统中的最小页面大小，将预定值写入动态位置，将与预定值相反的一系列值写入到所选择的页面大小位 页面存储器指针记录，当所选择的页面大小不同于初始页面大小时，以及将所选择的页面地址写入页面存储器指针记录的所选页面地址位。

公开(公告)号：US06625723B1

公开(公告)日：2003-09-23

申请号：US09348403

申请日：1999-07-07

申请人： Stephen J. Jourday ,  Adi Yoaz ,  Ronny Ronen ,  Michael Bekerman

发明人： Stephen J. Jourday ,  Adi Yoaz ,  Ronny Ronen ,  Michael Bekerman

IPC分类号： G06F938

CPC分类号： G06F9/3836 ,  G06F9/3824 ,  G06F9/3834 ,  G06F9/3838 ,  G06F9/384

摘要： A computer architecture for collapsing dependency graphs for colliding store and load instructions. Many-to-one mappings are provided between logical registers and physical registers, so that more than one logical register may map to the same physical register. For a load instruction that is predicted to collide with an earlier in-flight store instruction, the destination logical register of the load instruction is mapped to the same physical register to which the source logical register of the earlier in-flight store instruction is mapped. A many-to-one mapping may be realized by associating a counter with each physical register, so that the value of a counter indicates whether its associated physical counter is free.

摘要翻译： 用于折叠依赖关系图以用于存储和加载指令的计算机体系结构。 在逻辑寄存器和物理寄存器之间提供多对一映射，以便多个逻辑寄存器可映射到同一个物理寄存器。 对于预计与较早的飞行中存储指令相冲突的加载指令，加载指令的目的地逻辑寄存器被映射到映射了较早的飞行中存储指令的源逻辑寄存器的同一物理寄存器。 可以通过将计数器与每个物理寄存器相关联来实现多对一映射，使得计数器的值指示其相关联的物理计数器是否是空闲的。

公开(公告)号：US06594754B1

公开(公告)日：2003-07-15

申请号：US09348404

申请日：1999-07-07

申请人： Stephan J. Jourdan ,  Gad S. Sheaffer ,  Ronny Ronen

发明人： Stephan J. Jourdan ,  Gad S. Sheaffer ,  Ronny Ronen

IPC分类号： G06F9315

CPC分类号： G06F9/3857 ,  G06F9/30032 ,  G06F9/30167 ,  G06F9/384

摘要： A computer architecture to process move instructions by allowing multiple mappings between logical registers and the same physical register. In one embodiment, a counter is associated with each physical register to indicate when the physical register is free. A register-to-register move instruction is processed by mapping the logical destination register of the move instruction to the same physical register to which the logical source register of the move instruction is mapped. An immediate-to-register move instruction is processed by mapping the logical destination register of the move instruction to a physical register storing the immediate.

摘要翻译： 通过允许逻辑寄存器和同一物理寄存器之间的多个映射来处理移动指令的计算机体系结构。 在一个实施例中，计数器与每个物理寄存器相关联，以指示何时物理寄存器是空闲的。 通过将移动指令的逻辑目标寄存器映射到映射了移动指令的逻辑源寄存器的同一物理寄存器来处理寄存器到寄存器移动指令。 通过将移动指令的逻辑目标寄存器映射到存储立即数的物理寄存器来处理立即注册移动指令。

公开(公告)号：US06553469B2

公开(公告)日：2003-04-22

申请号：US10153920

申请日：2002-05-24

申请人： Stephan J. Jourdan ,  Ronny Ronen ,  Michael Bekerman

发明人： Stephan J. Jourdan ,  Ronny Ronen ,  Michael Bekerman

IPC分类号： G06F1200

CPC分类号： G06F9/3806 ,  G06F12/126

摘要： Apparatus and methods to filter memory record updates. A microprocessor can include a memory record update filter. The memory record update filter can include a table memory populated by a plurality of data entries. Each data entry can include a data tag field to store a data tag, a data field to store a data value, and a filter field to store a filter value. A first comparator can be in communication with the data tag field of the table memory and a data accessing information input to perform a data tag comparison. A second comparator can be in communication with the filter field of the table memory and a data value input. A control circuit can be in communication with the table memory, the first comparator, and the second comparator.

公开(公告)号：US06516405B1

公开(公告)日：2003-02-04

申请号：US09475646

申请日：1999-12-30

申请人： Stephan J. Jourdan ,  Freddy Gabbay ,  Ronny Ronen ,  Adi Yoaz

发明人： Stephan J. Jourdan ,  Freddy Gabbay ,  Ronny Ronen ,  Adi Yoaz

IPC分类号： G06F945

CPC分类号： G06F9/30094 ,  G06F9/383 ,  G06F9/3832 ,  G06F9/384 ,  G06F9/3842 ,  G06F9/3863

摘要： The present invention is directed to an apparatus and method for data collapsing based on control-flow speculation (conditional branch predictions). Because conditional branch outcomes are resolved based on actual data values, the conditional branch prediction provides potentially valuable insight into data values. Upon encountering a branch if equal instruction and this instruction is predicted as taken or a branch if not equal instruction and this instruction is predicted as not taken, this invention assumes that the two operands used to determine the conditional branch are equal. The data predictions are safe because a data misprediction means a conditional branch misprediction which results in a pipeline flush of the instructions following the conditional branch instruction including the data mispredictions.

摘要翻译： 本发明涉及一种基于控制流推测（条件分支预测）的数据压缩的装置和方法。 由于条件分支结果基于实际数据值进行解析，条件分支预测提供了对数据值的潜在有价值的洞察。 如果相等的指令遇到分支，并且如果不是相等的指令预测该指令或分支，并且该指令被预测为未被使用，则本发明假设用于确定条件分支的两个操作数相等。 数据预测是安全的，因为数据错误预测是指条件分支错误预测，导致在包括数据错误预测的条件分支指令之后的指令的流水线刷新。

公开(公告)号：US06438673B1

公开(公告)日：2002-08-20

申请号：US09475063

申请日：1999-12-30

申请人： Stephan J. Jourdan ,  Michael Bekerman ,  Ronny Ronen ,  Lihu Rappoport

发明人： Stephan J. Jourdan ,  Michael Bekerman ,  Ronny Ronen ,  Lihu Rappoport

IPC分类号： G06F1200

CPC分类号： G06F9/383 ,  G06F9/3455 ,  G06F9/3832 ,  G06F12/0862 ,  G06F2212/6024

摘要： A microprocessor having a correlated address predictor, and methods of performing correlated address prediction. A first table memory can be populated by a plurality of buffer entries. Each buffer entry can include a first buffer field to store a first tag based on an instruction pointer and a second buffer field to store an address history. A second table memory can be populated by a plurality of link entries. Each link entry can include a first link field to store a link tag based on an address history and a second link field to store a predicted address. A first comparator can be in communication with the first table memory and an instruction pointer input. A second comparator can be in communication with the first table memory and the second table memory. An output in communication with the second table memory.

摘要翻译： 具有相关地址预测器的微处理器，以及执行相关地址预测的方法。 第一表存储器可以由多个缓冲器入口填充。 每个缓冲器条目可以包括基于指令指针存储第一标签的第一缓冲区域和用于存储地址历史的第二缓冲区域。 第二表存储器可以由多个链接条目填充。 每个链接条目可以包括基于地址历史存储链接标签的第一链接字段和用于存储预测地址的第二链接字段。 第一比较器可以与第一表存储器和指令指针输入通信。 第二比较器可以与第一表存储器和第二表存储器通信。 与第二表存储器通信的输出。

公开(公告)号：US6134643A

公开(公告)日：2000-10-17

申请号：US979575

申请日：1997-11-26

申请人： Gershon Kedem ,  Ronny Ronen ,  Adi Yoaz

发明人： Gershon Kedem ,  Ronny Ronen ,  Adi Yoaz

IPC分类号： G06F12/08

CPC分类号： G06F12/0862 ,  G06F2212/6024

摘要： A microprocessor includes an execution engine, a prediction table cache, and a prefetch controller. The execution engine is adapted to issue a memory request. The memory request includes an identifier corresponding to a row location in an external main memory. The prediction table cache is adapted to store a plurality of entries defining an access history of previously encountered memory requests. The prediction table cache is indexed by the identifier. The prefetch controller is adapted to receive the memory request and generate at least one prefetch candidate based on the memory request and the access history. A method for prefetching data in a microprocessor includes receiving a memory request. The memory request includes an identifier corresponding to a row location in an external main memory. The memory request is compared to an access history of previously encountered memory requests. The access history is indexed by the identifier. At least one prefetch candidate is generated based on the memory request and the access history.

摘要翻译： 微处理器包括执行引擎，预测表缓存和预取控制器。 执行引擎适于发出存储器请求。 存储器请求包括对应于外部主存储器中的行位置的标识符。 预测表缓存适于存储定义先前遇到的存储器请求的访问历史的多个条目。 预测表缓存由标识符索引。 预取控制器适于接收存储器请求，并且基于存储器请求和访问历史来生成至少一个预取候选。 用于在微处理器中预取数据的方法包括接收存储器请求。 存储器请求包括对应于外部主存储器中的行位置的标识符。 将存储器请求与先前遇到的存储器请求的访问历史进行比较。 访问历史记录由标识符索引。 基于存储器请求和访问历史生成至少一个预取候选。