公开(公告)号：US12095461B2

公开(公告)日：2024-09-17

申请号：US18054978

申请日：2022-11-14

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Daisuke Moriyama

IPC: H03K19/17 ,  H03K19/0185 ,  H03K19/17736 ,  H03K19/17768

CPC classification number: H03K19/17768 ,  H03K19/018564 ,  H03K19/17744

Abstract: A semiconductor device includes: an arithmetic circuit that repeats an operation related to a cryptographic processing for the predetermined number of rounds; a holding circuit that holds data related to the number of rounds of an operation of the arithmetic circuit; a judgement circuit that determines whether the number of rounds is the predetermined number of rounds; and an output buffer circuit that outputs the arithmetic result data of the arithmetic circuit when the judgement circuit determines that the number of rounds is the predetermined number. It is configured to duplicate the holding circuit, and not to output the arithmetic result data when two outputs of the duplicated holding circuit are not matched.

公开(公告)号：US20240304680A1

公开(公告)日：2024-09-12

申请号：US18437947

申请日：2024-02-09

Applicant: Renesas Electronics Corporation

Inventor： Takahiro MARUYAMA ,  Tomoki AYANO ,  Yuya ABIKO

IPC: H01L29/40 ,  H01L29/423

CPC classification number: H01L29/401 ,  H01L29/407 ,  H01L29/4236

Abstract: A field plate electrode is formed in an inside of a trench via a first insulating film. Another part of the field plate electrode is selectively removed such that part of the field plate electrode is left as a lead portion. After the first insulating film is recessed, a protective film is formed on the first insulating film. A gate insulating film is formed in the inside of the trench, and a second insulating film is formed so as to cover the field plate electrode. A conductive film is formed on the gate insulating, second insulating film and protective films. A gate electrode is formed on the field plate electrode by removing the conductive film located in an outside of the trench. At this time, the conductive film formed on each of the protective film and the second insulating film, which are in contact with the lead portion, is removed.

公开(公告)号：US20240304566A1

公开(公告)日：2024-09-12

申请号：US18435425

申请日：2024-02-07

Applicant: Renesas Electronics Corporation

Inventor： Yuki YAMAMOTO ,  Hiroyuki ARIE

IPC: H01L23/00 ,  H01L21/265 ,  H01L21/768 ,  H01L23/522 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L23/562 ,  H01L21/26513 ,  H01L21/768 ,  H01L23/5226 ,  H01L29/66681 ,  H01L29/7816

Abstract: A semiconductor device includes a semiconductor substrate having a first main surface and a second main surface, a plurality of interlayer dielectric films, and a plurality of wiring layers stacked above the first main surface. Each of the plurality of interlayer dielectric films is interposed between two adjacent ones of the plurality of wiring layers and between one of the plurality of wiring layers closest to the first main surface in a first direction and the first main surface. A trench recessed toward the second main surface is formed on the first main surface. The trench includes a straight portion extending along a second direction. The plurality of wiring layers has a first wiring layer farthest from the first main surface in the first direction and a second wiring layer farthest from the first main surface next to the first wiring layer in the first direction.

公开(公告)号：US20240302294A1

公开(公告)日：2024-09-12

申请号：US18598075

申请日：2024-03-07

Applicant: Renesas Electronics Corporation

Inventor： Kaoru KOHIRA

IPC: G01N22/04 ,  H01L23/66

CPC classification number: G01N22/04 ,  H01L23/66 ,  H01L2223/6677

Abstract: A semiconductor device includes a transmission device and a reception device generating a demodulating signal by receiving the transmission signal via the measuring object from the antenna, and performing a processing to the demodulating signal. The transmission device is configured to start modulation at a first phase. The reception device stores a first phase and a physical quantity corresponding to a phase change amount in advance, estimate modulating signal start timing at which the reception signal switches from a non-modulation period to a modulation period based on a waveform of the demodulating signal; calculate a second phase that is a phase at the modulation start timing, calculates a variation to the second phase based on the stored first phase; and determine a physical quantity corresponding to the variation based on the physical quantity corresponding to a stored phase change amount.

公开(公告)号：US12087364B2

公开(公告)日：2024-09-10

申请号：US17547856

申请日：2021-12-10

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Masafumi Hayakawa

IPC: G11C16/16 ,  G11C16/08 ,  G11C16/34

CPC classification number: G11C16/16 ,  G11C16/08 ,  G11C16/3445

Abstract: A semiconductor device includes a flash memory including a plurality of electrically erasable memory cells and configured to output a verification result signal indicating whether erasing is succeeded or not, and a control block configured to control the flash memory. The control block includes a batch erasing range control circuit indicating a collectively erased range in the flash memory. When the verification result signal VR indicates failure of erasing of sectors in a first range specified by the batch erasing range control circuit after the erasing is executed, a second range for which erasing is to be executed again is calculated on the basis of a failure sector address that specifies a sector for which the erasing is failed and an end sector address that specifies an end of the first range, the specified second range is set to the batch erasing range control circuit, and erasing sectors in the second range is executed.

公开(公告)号：US12080716B2

公开(公告)日：2024-09-03

申请号：US18317500

申请日：2023-05-15

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Takaaki Tsunomura ,  Yoshiki Yamamoto ,  Masaaki Shinohara ,  Toshiaki Iwamatsu ,  Hidekazu Oda

IPC: H01L27/12 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/417

CPC classification number: H01L27/1203 ,  H01L27/1207 ,  H01L29/66477 ,  H01L29/66628 ,  H01L29/66651 ,  H01L29/7834 ,  H01L21/823418 ,  H01L21/823814 ,  H01L29/41783

Abstract: On a semiconductor substrate having an SOI region and a bulk silicon region formed on its upper surface, epitaxial layers are formed in source and drain regions of a MOSFET formed in the SOI region, and no epitaxial layer is formed in source and drain regions of a MOSFET formed in the bulk silicon region. By covering the end portions of the epitaxial layers with silicon nitride films, even when diffusion layers are formed by implanting ions from above the epitaxial layers, it is possible to prevent the impurity ions from being implanted down to a lower surface of a silicon layer.

公开(公告)号：US12073900B2

公开(公告)日：2024-08-27

申请号：US17900228

申请日：2022-08-31

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Haruyuki Okuda

IPC: G11C29/12 ,  G11C11/418

CPC classification number: G11C29/12005 ,  G11C11/418 ,  G11C2029/1202

Abstract: A semiconductor device includes memory cells, word lines, a row address decoder, word line drivers, a first switch transistor, and second switch transistors. The switch transistor is provided between the word line drivers and a power supply potential terminal. Each second switch transistor is provided between each word line and a reference potential terminal. The row address decoder activates all of decode signals corresponding to the memory cells to which a burn-in test is performed collectively. The first switch transistor has a lower driving capability than a total driving capability of two P-channel MOS transistors included in inverters of two word line drivers. Each second switch transistor has a lower driving capability than a driving capability of an N-channel MOS transistor included in the inverter of each word line driver.

公开(公告)号：US20240234262A9

公开(公告)日：2024-07-11

申请号：US18452845

申请日：2023-08-21

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Junichi NITA ,  Seiji HIRABAYASHI

IPC: H01L23/495 ,  H01L21/48

CPC classification number: H01L23/49548 ,  H01L21/4828 ,  H01L21/4842

Abstract: A common lead frame can be used for both a first package and a second package and has a planar shape according to specifications of each of a first chip used in the first package and a second chip used in the second package, and a thickness of at least a part of a lead portion through which any one of a first cutting line corresponding to an outer peripheral side of the first package and a second cutting line corresponding to an outer peripheral side of the second package passes is smaller than a thickness of a lead portion through which the first cutting line and the second cutting line do not pass.

公开(公告)号：US20240230751A9

公开(公告)日：2024-07-11

申请号：US18470820

申请日：2023-09-20

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yoshiaki TANAKA ,  Kouji NAKAJIMA

IPC: G01R31/28

CPC classification number: G01R31/2853

Abstract: A semiconductor device making it easy to detect disconnection in source wires and achieving a reduction in resistance and an inspection method for the semiconductor device are provided. A semiconductor device according to the present embodiment includes: a lead frame; a semiconductor chip on the lead frame; a source pad provided in the semiconductor chip; a plurality of source wires connected to the source pad; a disconnection detection wire connected to the source pad; source terminals connected to the plurality of source wires; and a disconnection detection terminal connected to the disconnection detection wire. One end of the disconnection detection wire is positioned in vicinity of a corner of the source pad closer to the disconnection detection terminal side.

公开(公告)号：US20240205550A1

公开(公告)日：2024-06-20

申请号：US18540643

申请日：2023-12-14

Applicant: Renesas Electronics Corporation

Inventor： Yuuji INAE

IPC: H04N23/80

CPC classification number: H04N23/80

Abstract: Reducing the increase in circuit area when processing images in each channel. Providing an image processing device that includes an input part for inputting images, an image processing part included in the first channel, an image processing part included in the second channel, a control part that delays the output from the second channel for a time corresponding to the processing time of the first channel and the processing time of the second channel, and an output part that outputs the output from the first channel and the output from the second channel in a first-in-first-out manner.