公开(公告)号：US07115464B2

公开(公告)日：2006-10-03

申请号：US10259016

申请日：2002-09-27

Applicant: Rolf Stephan ,  Manfred Horstmann ,  Karsten Wieczorek

Inventor： Rolf Stephan ,  Manfred Horstmann ,  Karsten Wieczorek

IPC: H01L21/8238 ,  H01L21/336 ,  H01L21/76 ,  H01L21/3205

CPC classification number: H01L21/324 ,  H01L21/28052 ,  H01L21/823835 ,  H01L21/823842

Abstract: In a method for fabricating a semiconductor device different types of a metal-semiconductor compound are formed on or in at least two different conductive semiconductor regions so that for each semiconductor region the metal-semiconductor compound region may be formed to obtain an optimum overall performance of the semiconductor device. On one of the two semiconductor regions, the metal-semiconductor compound is formed of at least two different metal layers, whereas the metal-semiconductor compound in or on the other semiconductor region is formed from a single metal layer.

公开(公告)号：US06846708B2

公开(公告)日：2005-01-25

申请号：US10601717

申请日：2003-06-23

Applicant: Thomas Feudel ,  Manfred Horstmann ,  Rolf Stephan

Inventor： Thomas Feudel ,  Manfred Horstmann ,  Rolf Stephan

IPC: H01L21/265 ,  H01L21/336 ,  H01L21/00 ,  H01L21/84

CPC classification number: H01L29/6659 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/26586

Abstract: An implanting process for amorphizing a crystalline substrate is proposed according to the present invention. In particular, according to the present invention, amorphous regions are formed in a substrate by exposing the substrate to an ion beam which is kept at a tilt angle between 10 and 80 degrees with respect to the surface of the substrate. Accordingly, ion channeling during subsequent implanting processes is prevented not only in the vertical direction but also in the horizontal direction so that doped regions exhibiting optimum doping profile tailoring may be realized.

Abstract translation: 根据本发明提出了一种用于非晶化晶体衬底的注入工艺。 特别地，根据本发明，通过将衬底暴露于相对于衬底的表面保持在10至80度之间的倾斜角的离子束，在衬底中形成非晶区域。 因此，不仅在垂直方向上而且在水平方向上都防止后续植入过程中的离子通道化，从而可以实现具有最佳掺杂分布调整的掺杂区域。

公开(公告)号：US06822430B2

公开(公告)日：2004-11-23

申请号：US10602577

申请日：2003-06-24

Applicant: Thomas Feudel ,  Manfred Horstmann ,  Rolf Stephan

Inventor： Thomas Feudel ,  Manfred Horstmann ,  Rolf Stephan

IPC: G01N2700

CPC classification number: G01R31/2648 ,  G01R31/2621 ,  G06F17/5018 ,  H01L22/34

Abstract: A cost-efficient and reliable method for assessing lateral dopant profiles includes the estimation of a reference profile formed below a gate structure of a transistor device. The overlap capacitance is then determined for at least two different overlaps, created by different spacer widths, and the lateral extension of a dopant profile to be measured, is estimated on the basis of a relationship between overlap capacitance and spacer width for the reference dopant profile.

Abstract translation: 用于评估横向掺杂物分布的成本有效且可靠的方法包括在晶体管器件的栅极结构之下形成的参考分布的估计。 然后基于重叠电容和参考掺杂物分布的间隔物宽度之间的关系来估计重叠电容对于由不同的间隔物宽度产生的至少两个不同的重叠，并且待测量的掺杂物分布的横向延伸。 。

公开(公告)号：US06306698B1

公开(公告)日：2001-10-23

申请号：US09558963

申请日：2000-04-25

Applicant: Karsten Wieczorek ,  Michael Raab ,  Rolf Stephan

Inventor： Karsten Wieczorek ,  Michael Raab ,  Rolf Stephan

IPC: H01L21336

CPC classification number: H01L29/66507

Abstract: The present invention is directed to a semiconductor device (100) having enhanced electrical performance characteristics, and a method of making such a device. In one illustrative embodiment, the semiconductor device (100) is comprised of a polysilicon gate electrode (104) positioned above a gate insulation layer (105), a plurality of source/drain regions (109) formed in a semiconducting substrate (101), a first metal silicide region (111A) positioned above the gate electrode (104), a second metal silicide region (107) positioned above each of the source/drain regions (109), wherein the first metal silicide region (111A) is approximately 2-10 times thicker than each of the second metal silicide regions (107). In one illustrative embodiment, the inventive method disclosed herein comprises forming a first layer of a refractory metal (110) above a layer of polysilicon (104), and converting the refractory metal layer (110) to a metal suicide layer (111), and patterning the metal silicide layer (111) and the gate electrode layer (104) to form a metal silicide region (111A) above the gate electrode (104). The method further comprises forming a plurality of source/drain regions (109) in the substrate (101), forming a second layer comprised of a refractory metal above at least the gate stack (122) and the source/drain regions (109). The method concludes with converting at least a portion of the second layer of refractory metal to a second metal silicide region above each of the source/drain regions (109).

Abstract translation: 本发明涉及具有增强的电气性能特性的半导体器件（100）以及制造这种器件的方法。 在一个说明性实施例中，半导体器件（100）由位于栅极绝缘层（105）上方的多晶硅栅电极（104），形成在半导体衬底（101）中的多个源极/漏极区域（109） 位于栅电极（104）上方的第一金属硅化物区（111A），位于源极/漏极区（109）之上的第二金属硅化物区（107），其中第一金属硅化物区（111A）约为2 比第二金属硅化物区域（107）的厚度大10〜10倍。 在一个示例性实施例中，本文公开的本发明的方法包括在多晶硅层（104）上方形成难熔金属（110）的第一层，并将难熔金属层（110）转化为金属硅化物层（111），以及 图案化金属硅化物层（111）和栅电极层（104）以在栅电极（104）上方形成金属硅化物区域（111A）。 该方法还包括在衬底（101）中形成多个源极/漏极区（109），在至少栅极堆叠（122）和源极/漏极区（109）之上形成由难熔金属组成的第二层。 该方法的结论是将难熔金属的第二层的至少一部分转换成源极/漏极区域（109）之上的第二金属硅化物区域。

公开(公告)号：US08119461B2

公开(公告)日：2012-02-21

申请号：US12916681

申请日：2010-11-01

Applicant: Martin Trentzsch ,  Thorsten Kammler ,  Rolf Stephan

Inventor： Martin Trentzsch ,  Thorsten Kammler ,  Rolf Stephan

IPC: H01L21/335 ,  H01L21/8232

CPC classification number: H01L21/28158 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/785

Abstract: By performing a heat treatment on the basis of a hydrogen ambient, exposed silicon-containing surface portions may be reorganized prior to the formation of gate dielectric materials. Hence, the interface quality and the material characteristics of the gate dielectrics may be improved, thereby reducing negative bias temperature instability effects in highly scaled P-channel transistors.

Abstract translation: 通过基于氢环境进行热处理，暴露的含硅表面部分可以在形成栅极电介质材料之前重组。 因此，可以提高栅极电介质的界面质量和材料特性，从而降低高标度P沟道晶体管中的负偏压温度不稳定性的影响。

公开(公告)号：US20120025276A1

公开(公告)日：2012-02-02

申请号：US13251532

申请日：2011-10-03

Applicant: Rolf Stephan ,  Markus Forsberg ,  Gert Burbach ,  Anthony Mowry

Inventor： Rolf Stephan ,  Markus Forsberg ,  Gert Burbach ,  Anthony Mowry

IPC: H01L29/66 ,  H01L21/66

CPC classification number: H01L27/0629 ,  H01L21/823807 ,  H01L27/1203

Abstract: By incorporating germanium material into thermal sensing diode structures, the sensitivity thereof may be significantly increased. In some illustrative embodiments, the process for incorporating the germanium material may be performed with high compatibility with a process flow for incorporating a silicon/germanium material into P-channel transistors of sophisticated semiconductor devices. Hence, temperature control efficiency may be increased with reduced die area consumption.

Abstract translation: 通过将锗材料结合到热敏二极管结构中，其灵敏度可以显着增加。 在一些说明性实施例中，可以与用于将硅/锗材料并入复杂半导体器件的P沟道晶体管的工艺流程具有高兼容性来执行用于并入锗材料的工艺。 因此，可以降低模具面积消耗来提高温度控制效率。

公开(公告)号：US07745334B2

公开(公告)日：2010-06-29

申请号：US11736939

申请日：2007-04-18

Applicant: Patrick Press ,  Karla Romero ,  Martin Trentzsch ,  Karsten Wieczorek ,  Thomas Feudel ,  Markus Lenski ,  Rolf Stephan

Inventor： Patrick Press ,  Karla Romero ,  Martin Trentzsch ,  Karsten Wieczorek ,  Thomas Feudel ,  Markus Lenski ,  Rolf Stephan

IPC: H01L21/302 ,  H01L21/461

CPC classification number: H01L21/268 ,  H01L21/823807 ,  H01L27/11 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/7833 ,  H01L29/7843

Abstract: By performing sophisticated anneal techniques, such as laser anneal, flash anneal and the like, for a metal silicide formation, such as nickel silicide, the risk of nickel silicide defects in sensitive device regions, such as SRAM pass gates, may be significantly reduced. Also, the activation of dopants may be performed in a highly localized manner, so that undue damage of gate insulation layers may be avoided when activating and re-crystallizing drain and source regions.

Abstract translation: 通过对诸如硅化镍之类的金属硅化物形成进行诸如激光退火，闪光退火等复杂的退火技术，可以显着地减少诸如SRAM通孔之类的敏感器件区域中的硅化镍缺陷的风险。 此外，可以以高度局部化的方式执行掺杂剂的激活，使得当激活和再结晶漏极和源极区域时，可以避免栅极绝缘层的过度损坏。

公开(公告)号：US20100077839A1

公开(公告)日：2010-04-01

申请号：US12507986

申请日：2009-07-23

Applicant: Martin Trentzsch ,  Stephan Kronholz ,  Rolf Stephan

Inventor： Martin Trentzsch ,  Stephan Kronholz ,  Rolf Stephan

IPC: G01N33/00 ,  G01N27/00 ,  H01L21/306

CPC classification number: G01N27/221 ,  G01N27/226

Abstract: By providing a tool internal sensor device in a process tool in a semiconductor facility, metal contamination may be monitored in situ, thereby avoiding or at least significantly reducing the requirement for sophisticated sample preparation techniques, such as vapor phase decomposition tests in combination with subsequent analysis procedures. Thus, a full time inspection of process tools may be accomplished.

Abstract translation: 通过在半导体设备中的工艺工具中提供工具内部传感器装置，可以原位监测金属污染，从而避免或至少显着地降低复杂的样品制备技术的需要，例如与后续分析相结合的气相分解测试 程序。 因此，可以完成对过程工具的全面检查。

公开(公告)号：US07563731B2

公开(公告)日：2009-07-21

申请号：US11739279

申请日：2007-04-24

Applicant: Christoph Schwan ,  Manfred Horstmann ,  Kai Frohberg ,  Rolf Stephan

Inventor： Christoph Schwan ,  Manfred Horstmann ,  Kai Frohberg ,  Rolf Stephan

IPC: H01L21/31 ,  H01L21/469

CPC classification number: H01L29/7843 ,  H01L21/823807 ,  H01L21/823828 ,  Y10S438/902

Abstract: By increasing the transistor topography after forming a first layer of highly stressed dielectric material, additional stressed material may be added, thereby efficiently increasing the entire layer thickness of the stressed dielectric material. The corresponding increase of device topography may be accomplished on the basis of respective placeholder structures or dummy gates, wherein well-established gate patterning processes may be used or wherein nano-imprint techniques may be employed. Hence, in some illustrative embodiments, a significant increase of strain may be obtained on the basis of well-established process techniques.

Abstract translation: 通过在形成第一层高应力电介质材料之后增加晶体管形貌，可以添加额外的应力材料，从而有效地增加应力介电材料的整个层厚度。 可以基于相应的占位符结构或伪栅极来实现器件形貌的相应增加，其中可以使用完全确定的栅极图案化工艺，或者可以采用纳米压印技术。 因此，在一些说明性实施例中，可以基于公认的工艺技术获得应变的显着增加。

公开(公告)号：US20080081486A1

公开(公告)日：2008-04-03

申请号：US11739279

申请日：2007-04-24

Applicant: Christoph Schwan ,  Manfred Horstmann ,  Kai Frohberg ,  Rolf Stephan

Inventor： Christoph Schwan ,  Manfred Horstmann ,  Kai Frohberg ,  Rolf Stephan

IPC: H01L21/31

CPC classification number: H01L29/7843 ,  H01L21/823807 ,  H01L21/823828 ,  Y10S438/902

Abstract: By increasing the transistor topography after forming a first layer of highly stressed dielectric material, additional stressed material may be added, thereby efficiently increasing the entire layer thickness of the stressed dielectric material. The corresponding increase of device topography may be accomplished on the basis of respective placeholder structures or dummy gates, wherein well-established gate patterning processes may be used or wherein nano-imprint techniques may be employed. Hence, in some illustrative embodiments, a significant increase of strain may be obtained on the basis of well-established process techniques.

Abstract translation: 通过在形成第一层高应力电介质材料之后增加晶体管的形貌，可添加额外的应力材料，从而有效地增加应力介电材料的整个层厚度。 可以基于相应的占位符结构或伪栅极来实现器件形貌的相应增加，其中可以使用完全确定的栅极图案化工艺，或者可以采用纳米压印技术。 因此，在一些说明性实施例中，可以基于公认的工艺技术获得应变的显着增加。