Abstract:
This invention concerns a resynchronization method by a receiver of a received stream of groups of bits, comprising: detecting a synchronization loss (S10), and then iterating (S11 to S17) checks over different bits until a first bit of a group of bits is found (S14), the most probable first bit being checked first, wherein the checks are iterated in a checking order of bits different from a chronological reception order, so as to check earlier at least one of most probable first bits, different from the most probable first bit, so as to shorten average resynchronization time.
Abstract:
Continuous-time MASH sigma-delta ADC with a first modulator with 1.5 bit and a second modulator with 1 bit each receiving also the feedback from the other modulator. Sampling is at higher rate at the second modulator and decimation is performed before summing its output to the output of the first modulator.
Abstract:
A matrix for use with a radio transceiver having at least two signal sources is provided. The matrix comprises for each selected set of two or more signal sources, a list of combinations of harmonics of the signal sources, the combinations of harmonics each having a predicted amplitude greater than a predetermined threshold, and a frequency within a defined range related to a frequency range of one of the signal sources. Further, methods for generating such matrix and methods for avoiding spurs are provided.
Abstract:
Disclosed herein is a passive, voltage mode transmitter assembly and method of operation. The passive, voltage mode transmitter assembly comprises a baseband filter configured to filter a source baseband signal, a harmonics filter, connected to the baseband filter, configured to remove harmonics from the filtered, source baseband signal, a passive, voltage mode mixer, connected to the harmonics filter, configured to up-convert an output of the harmonics filter to a radio signal, and a power amplifier, connected to the passive, voltage mode mixer, configured to amplify the radio signal.
Abstract:
The invention concerns a method of evaluating by a user equipment a need for handover between cells in a cellular network, comprising a step (S1) of estimating a risk (R) of making an ineffective handover, and when said estimated risk (R) is above a threshold (S), a step (S2) of changing the value of at least one handover trigger parameter so as to reduce, for given handover attractiveness parameters respectively received from cells, the future rate of handover to be made by user equipment.
Abstract:
The invention provides circuitry integrated into a silicon chip that measures aspects of an RF signal on a transmission line in order to provide data that is ultimately used by an antenna tuner circuit to substantially match the impedance of the antenna with that of the transmission line providing the RF frequency to be transmitted.
Abstract:
A Reference Signal Received Power (RSRP) value is produced from a received Orthogonal Frequency Division Multiplexed (OFDM) signal that comprises a plurality of reference symbols located at known sub-carrier frequencies and times within the received OFDM signal. RSRP value production involves, for each hypothesized error state selected from a plurality of different hypothesized error states, ascertaining a corresponding hypothesized RSRP value, and then using the hypothesized RSRP values as a basis for determining a value for use as the produced RSRP value (e.g., by selecting a maximum one of the hypothesized RSRP values as the produced RSRP value). In this technology, each of the hypothesized error states is a hypothesized frequency error paired with a hypothesized timing error and the corresponding hypothesized RSRP value is produced by adjusting one or more measured channel estimates as a function of the hypothesized error state.
Abstract:
The present invention relates to a signal synchronization circuit comprising at least one synchronizer (2.1-2.2) comprising a number N of series connected clock delay elements (3.1-3.3), N being equal to or greater than unity and a clock signal generator (1) arranged for generating a modulated clock signal adapted to clock the clock delay element (3.1-3.3) or elements of the at least one synchronizer (2.1-2.2). The clock generator (1) is arranged to receive a clock signal (5) and at least one operating value (6) and to generate the modulated clock signal (1 out) from the clock signal (5) modified based on the operating value (6).
Abstract:
The present subject matter discloses a system and a method for processing of channel coefficients of networks. In one embodiment, the method includes ascertaining at least one probable synchronization position of a received sequence and projecting, by oblique projection, at least one given noise basis vector spanning a given noise space onto the null space, so as to determine a channel impulse response at the at least one probable synchronization position. Based on a criterion related to the channel impulse response, a synchronization point for the received sequence is identified from the at least one probable synchronization position. The method also includes determining the noise contribution at the synchronization point and determining the noise coefficient of the at least one given noise basis vector based on the noise contribution so as to recover a signal substantially similar to the originally transmitted signal.
Abstract:
The present subject matter discloses a system and a method for estimating a frequency offset in communication devices. In one embodiment, the method of estimating a frequency offset in a communication device comprises generating a reconstructed signal based at least in part on a channel impulse response (CIR) corresponding to a received signal. Further, a normalization matrix is determined for the reconstructed signal. Thereafter, based at least in part on the normalization matrix and the reconstructed signal, the frequency offset is estimated such that the frequency offset corresponds to a maximum normalized-correlation between the reconstructed signal and the received signal.