公开(公告)号：US5666321A

公开(公告)日：1997-09-09

申请号：US522869

申请日：1995-09-01

Applicant: Scott Schaefer

Inventor： Scott Schaefer

IPC: G11C7/10 ,  G11C8/00 ,  G11C8/06 ,  G11C11/408 ,  G11C7/00

CPC classification number: G11C7/22 ,  G11C11/4076 ,  G11C11/4082 ,  G11C11/4087 ,  G11C7/1018 ,  G11C7/1027 ,  G11C7/1072 ,  G11C8/06 ,  G11C8/10 ,  G11C8/18

Abstract: Disclosed is a synchronous DRAM memory module with control circuitry that allows the memory module to operate partially asynchronously. Specifically, a circuit is disclosed which utilizes address transition detection to begin decoding the column-address immediately after a new column-address is present on the address bus lines and without waiting for the column-address strobe signal to synchronize with the rising or falling edge of the synchronizing clock signal. Also disclosed is a manner of controlling the latching circuitry whereby each new column-address may be decoded and held within a buffer until the column-address strobe signal notifies the circuitry that the column-address is correct and is to be input into the microprocessor. Thus, each new column-address will be decoded immediately after it is present on the address lines and undesired column-addresses will be discarded, while desired column-addresses are input into the memory array bank immediately upon the presence of the column-address strobe which denotes that the column-address is final. The present invention improves the access times of read and write operations in synchronous DRAM memory by up to a complete clock cycle.

Abstract translation: 公开了具有控制电路的同步DRAM存储器模块，其允许存储器模块部分地异步操作。 具体地，公开了一种电路，其利用地址转换检测在地址总线上存在新的列地址之后立即开始对列地址进行解码，而不等待列地址选通信号与上升沿或下降沿同步 的同步时钟信号。 还公开了一种控制锁存电路的方式，由此每个新的列地址可以被解码并保持在缓冲器中，直到列地址选通信号通知电路列地址是正确的并且要被输入微处理器。 因此，每个新的列地址在它存在于地址线上之后将立即被解码，并且不期望的列地址将被丢弃，而在列地址选通存在时，期望的列地址被立即输入到存储器阵列组中 这表示列地址是final。 本发明提高了同步DRAM存储器中的读写操作的访问时间，直到完整的时钟周期。

公开(公告)号：US07411857B2

公开(公告)日：2008-08-12

申请号：US11516848

申请日：2006-09-07

Applicant: Scott Schaefer

Inventor： Scott Schaefer

IPC: G11C5/14

CPC classification number: G11C5/14 ,  G11C5/143 ,  G11C7/1066 ,  G11C7/22 ,  G11C7/222 ,  G11C11/4074 ,  G11C11/4076 ,  G11C2207/2227

Abstract: Apparatus for reducing the power consumed by a memory device selectively activates a power saving mode in which operation of a delay compensation circuit may be suspended during an active power down mode of operation.

Abstract translation: 用于降低存储器件消耗的功率的装置选择性地启动在有功断电操作模式期间可以暂停延迟补偿电路的操作的功率节省模式。

公开(公告)号：US07333384B2

公开(公告)日：2008-02-19

申请号：US11338155

申请日：2006-01-24

Applicant: Jeffery W. Janzen ,  Scott Schaefer ,  Todd D. Farrell

Inventor： Jeffery W. Janzen ,  Scott Schaefer ,  Todd D. Farrell

IPC: G11C17/18

CPC classification number: G11C11/4074 ,  G11C5/00 ,  G11C5/143 ,  G11C7/04 ,  G11C16/20 ,  G11C29/02 ,  G11C29/028 ,  G11C2029/4402 ,  G11C2029/5006

Abstract: Methods of configuring a system. More specifically, operating current values corresponding to respective memory devices of memory module may be stored in programmable elements, such as antifuses, located on the memory device, during fabrication. The operating current values may be read from and/or stored in a non-volatile memory device on the memory module. Once the memory module is incorporated into a system, the programmable elements on the memory devices and/or the non-volatile memory device on the memory module may be accessed such that the system can be configured to optimally operate in accordance with the operating current values measured for each memory device in the system.

Abstract translation: 配置系统的方法 更具体地，对应于存储器模块的各个存储器件的工作电流值可以在制造期间存储在位于存储器件上的可编程元件，例如反熔丝。 操作电流值可以从存储器模块中的非易失性存储器件读取和/或存储在存储器模块中的非易失性存储器件中。 一旦存储器模块被并入到系统中，可以访问存储器模块上的可编程元件和/或存储器模块上的非易失性存储器设备，使得可以将系统配置为根据工作电流值进行最佳操作 测量系统中的每个存储设备。

公开(公告)号：US20070189106A1

公开(公告)日：2007-08-16

申请号：US11648903

申请日：2007-01-03

Applicant: Christopher Johnson ,  Scott Schaefer

Inventor： Christopher Johnson ,  Scott Schaefer

IPC: G11C8/00

CPC classification number: G11C7/225 ,  G11C7/1045 ,  G11C7/22 ,  G11C8/18 ,  G11C2207/2227

Abstract: The present invention provides a memory device having a mode register with a selectable bit which sets the memory device to operate with a selected one of a plurality of possible clock input signals, for example, a single clock input or differential clock input.

Abstract translation: 本发明提供一种存储器件，其具有具有可选位的模式寄存器，该可选位将存储器件设置为使用多个可能的时钟输入信号（例如单个时钟输入或差分时钟输入）中选定的一个进行操作。

公开(公告)号：US20070002663A1

公开(公告)日：2007-01-04

申请号：US11516848

申请日：2006-09-07

Applicant: Scott Schaefer

Inventor： Scott Schaefer

IPC: G11C5/14

CPC classification number: G11C5/14 ,  G11C5/143 ,  G11C7/1066 ,  G11C7/22 ,  G11C7/222 ,  G11C11/4074 ,  G11C11/4076 ,  G11C2207/2227

Abstract: Apparatus for reducing the power consumed by a memory device selectively activates a power saving mode in which operation of a delay compensation circuit may be suspended during an active power down mode of operation.

Abstract translation: 用于降低存储器件消耗的功率的装置选择性地启动在有功断电操作模式期间可以暂停延迟补偿电路的操作的功率节省模式。

公开(公告)号：US20060123221A1

公开(公告)日：2006-06-08

申请号：US11338155

申请日：2006-01-24

Applicant: Jeffery Janzen ,  Scott Schaefer ,  Todd Farrell

Inventor： Jeffery Janzen ,  Scott Schaefer ,  Todd Farrell

IPC: G06F15/177

CPC classification number: G11C11/4074 ,  G11C5/00 ,  G11C5/143 ,  G11C7/04 ,  G11C16/20 ,  G11C29/02 ,  G11C29/028 ,  G11C2029/4402 ,  G11C2029/5006

Abstract: Methods of configuring a system. More specifically, operating current values corresponding to respective memory devices of memory module may be stored in programmable elements, such as antifuses, located on the memory device, during fabrication. The operating current values may be read from and/or stored in a non-volatile memory device on the memory module. Once the memory module is incorporated into a system, the programmable elements on the memory devices and/or the non-volatile memory device on the memory module may be accessed such that the system can be configured to optimally operate in accordance with the operating current values measured for each memory device in the system.

Abstract translation: 配置系统的方法 更具体地，对应于存储器模块的各个存储器件的工作电流值可以在制造期间存储在位于存储器件上的可编程元件，例如反熔丝。 操作电流值可以从存储器模块中的非易失性存储器件读取和/或存储在存储器模块中的非易失性存储器件中。 一旦存储器模块被并入到系统中，可以访问存储器模块上的可编程元件和/或存储器模块上的非易失性存储器设备，使得可以将系统配置为根据工作电流值进行最佳操作 测量系统中的每个存储设备。

公开(公告)号：US20060062056A1

公开(公告)日：2006-03-23

申请号：US11270578

申请日：2005-11-10

Applicant: Christopher Johnson ,  Scott Schaefer

Inventor： Christopher Johnson ,  Scott Schaefer

IPC: G11C8/00 ,  G11C7/00

CPC classification number: G11C7/225 ,  G11C7/1045 ,  G11C7/22 ,  G11C8/18 ,  G11C2207/2227

Abstract: The present invention provides a memory device having a mode register with a selectable bit which sets the memory device to operate with a selected one of a plurality of possible clock input signals, for example, a single clock input or differential clock input.

公开(公告)号：US06862202B2

公开(公告)日：2005-03-01

申请号：US10669663

申请日：2003-09-23

Applicant: Scott Schaefer

Inventor： Scott Schaefer

IPC: G11C7/22 ,  G11C8/12 ,  G11C5/02

CPC classification number: G11C7/22 ,  G11C8/12

Abstract: A memory module for an electronic device provides means for reducing the amount of power necessary to access a desired number of data bits. This provides a design of memory modules which requires fewer DRAMs to be turned on during a read or write cycle than present module designs, thereby using much less power.

Abstract translation: 用于电子设备的存储器模块提供用于减少访问所需数量的数据位所需的功率量的装置。 这提供了存储器模块的设计，其在读取或写入周期期间比当前模块设计要求更少的DRAM被接通，从而使用更少的功率。

公开(公告)号：US06819599B2

公开(公告)日：2004-11-16

申请号：US10210483

申请日：2002-08-01

Applicant: Scott Schaefer

Inventor： Scott Schaefer

IPC: G11C700

CPC classification number: G11C7/1066 ,  G11C7/1045 ,  G11C7/1051 ,  G11C7/22 ,  G11C7/222 ,  G11C11/4076 ,  G11C11/4096

Abstract: A method and apparatus are provided for programming a data strobe (DQS) preamble in a memory by loading a defined set of bits into one or more registers of the memory, where one or more bits are formatted specifically for enabling the data strobe preamble. At least one of the bits is used to enable a data strobe preamble as either a default data strobe preamble of the memory or as a reduced data strobe preamble with a time length set equal to a fraction of the default preamble or a fraction of a clock cycle. The enabling bit can be used to provide a input for generating a delay that provides a delayed signal to drivers of the memory for producing a reduced data strobe preamble and for sequencing or driving data to be read out of the memory. The reduced data strobe preamble can also be used for writing data into the memory.

Abstract translation: 提供了一种方法和装置，用于通过将定义的一组位加载到存储器的一个或多个寄存器中来对存储器中的数据选通（DQS）前导码进行编程，其中一个或多个位被格式化以用于启用数据选通前导码。 这些位中的至少一个用于使数据选通前同步码作为存储器的默认数据选通前导码，或者作为缩减数据选通前导，其时间长度设置为等于默认前导码的一部分或时钟的一部分 周期。 使能位可以用于提供用于产生延迟的输入，该延迟向存储器的驱动器提供延迟的信号，用于产生减少的数据选通前导码，并用于排序或驱动要从存储器读出的数据。 缩减数据选通前导码也可用于将数据写入存储器。

公开(公告)号：US06693837B2

公开(公告)日：2004-02-17

申请号：US10128936

申请日：2002-04-23

Applicant: Scott Schaefer ,  Todd D. Farrell

Inventor： Scott Schaefer ,  Todd D. Farrell

IPC: G11C700

CPC classification number: G11C11/406

Abstract: A system and method are disclosed to add logic to the self-refresh control logic presently employed in DRAM devices to ensure that, upon transitions between self-refresh mode and operational mode, at least one row of memory cells due to be refreshed is refreshed during the wait state following issuance of the transition command. Conducting this refresh during this existing wait state eliminates both the concern as to whether rows have been refreshed within the mandated refresh interval and the time required to execute an auto-refresh of at least one row upon completion of the transition.

Abstract translation: 公开了一种系统和方法，用于向当前在DRAM设备中使用的自刷新控制逻辑添加逻辑，以确保在自刷新模式和操作模式之间的转换时，在刷新期间至少一行存储器单元被刷新 发布转换命令后的等待状态。 在此现有等待状态期间执行此刷新消除了在强制刷新间隔内刷新行是否已被刷新以及完成转换后执行至少一行自动刷新所需的时间的担忧。