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91 条记录 (耗时 0.015 秒)

    Semiconductor device with partial passivation layer
    31.
    发明授权
    Semiconductor device with partial passivation layer 有权
    具有部分钝化层的半导体器件

    公开(公告)号：US06313538B1

    公开(公告)日：2001-11-06

    申请号：US09489479

    申请日：2000-01-21

    申请人： Christian Zistl ,  Paul R. Besser ,  Eric M. Apelgren ,  Nicholas J. Kepler ,  Srikanteswara Dakshina-Murthy

    发明人： Christian Zistl ,  Paul R. Besser ,  Eric M. Apelgren ,  Nicholas J. Kepler ,  Srikanteswara Dakshina-Murthy

    IPC分类号： H01L2348

    CPC分类号： H01L23/5329 ,  H01L21/76801 ,  H01L21/76834 ,  H01L23/3171 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor device includes a first dielectric layer, a plurality of conductive interconnections formed in the first dielectric layer, a patterned passivation layer formed above the conductive interconnections, and a second dielectric layer formed above and in contact with the passivation layer and the first dielectric layer. A method for forming a semiconductor device includes providing a base layer, forming a first dielectric layer over the base layer, forming a plurality of conductive interconnections in the first dielectric layer, forming a patterned passivation layer above the conductive interconnections, and forming a second dielectric layer above and in contact with the passivation layer and the first dielectric layer.

    摘要翻译： 半导体器件包括第一电介质层，形成在第一电介质层中的多个导电互连，形成在导电互连之上的图案化钝化层，以及形成在钝化层和第一介电层上方并与钝化层接触的第二介电层 。 一种用于形成半导体器件的方法包括提供基底层，在基底层上形成第一介电层，在第一介电层中形成多个导电互连，在导电互连之上形成图案化的钝化层，以及形成第二电介质 并且与钝化层和第一介电层接触。

    Combination of non-lithographic shrink techniques and trim process for gate formation and line-edge roughness reduction
    33.
    发明授权
    Combination of non-lithographic shrink techniques and trim process for gate formation and line-edge roughness reduction 有权
    非平版收缩技术和修剪过程的组合，用于栅极形成和线边缘粗糙度降低

    公开(公告)号：US07405032B1

    公开(公告)日：2008-07-29

    申请号：US10645364

    申请日：2003-08-21

    申请人： Gilles Amblard ,  Srikanteswara Dakshina-Murthy ,  Bhanwar Singh

    发明人： Gilles Amblard ,  Srikanteswara Dakshina-Murthy ,  Bhanwar Singh

    IPC分类号： G01B11/30 ,  G01B11/00 ,  G03C5/00

    CPC分类号： G01B11/30 ,  G03F7/40

    摘要： The present invention relates generally to photolithographic systems and methods, and more particularly to systems and methodologies that facilitate the reduction of line-edge roughness (LER) during gate formation in an integrated circuit.Systems and methods are disclosed for improving critical dimension (CD) of photoresist lines, comprising a non-lithographic shrink component that facilitates mitigating LER, and a trim etch component that facilitates achieving and/or restoring a target critical dimension.

    摘要翻译： 本发明一般涉及光刻系统和方法，更具体地涉及有助于在集成电路中形成栅极期间减少线边缘粗糙度（LER）的系统和方法。 公开了用于改善光致抗蚀剂线的临界尺寸（CD）的系统和方法，其包括有助于减轻LER的非光刻收缩组分，以及有助于实现和/或恢复目标临界尺寸的修剪蚀刻部件。

    System and method for imprint lithography to facilitate dual damascene integration in a single imprint act
    38.
    发明授权
    System and method for imprint lithography to facilitate dual damascene integration in a single imprint act 有权
    用于压印光刻的系统和方法，以便于在单一印记法中双重镶嵌一体化

    公开(公告)号：US07148142B1

    公开(公告)日：2006-12-12

    申请号：US10874500

    申请日：2004-06-23

    申请人： Srikanteswara Dakshina-Murthy ,  Bhanwar Singh ,  Khoi A. Phan

    发明人： Srikanteswara Dakshina-Murthy ,  Bhanwar Singh ,  Khoi A. Phan

    IPC分类号： H01L21/44

    CPC分类号： G03F7/0002 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/76807 ,  H01L21/76817 ,  H01L2221/1021

    摘要： A system and method are provided to facilitate dual damascene interconnect integration in a single imprint step. The method provides for creation of a translucent imprint mold with three-dimensional features comprising the dual damascene pattern to be imprinted. The imprint mold is brought into contact with a photopolymerizable organosilicon imaging layer deposited upon a transfer layer which is spin coated or otherwise deposited upon a dielectric layer of a substrate. When the photopolymerizable layer is exposed to a source of illumination, it cures with a structure matching the dual damascene pattern of the imprint mold. A halogen breakthrough etch followed by oxygen transfer etch transfer the vias from the imaging layer into the transfer layer. A second halogen breakthrough etch followed by a second oxygen transfer etch transfer the trenches from the imaging layer into the transfer layer. A dielectric etch transfers the pattern from the transfer layer into the dielectric layer. A metal fill process then fills the dual damascene openings of the dielectric layer with metal.

    摘要翻译： 提供了一种系统和方法，以便在单个压印步骤中促进双镶嵌互连集成。 该方法提供了具有三维特征的半透明压印模具的创建，该三维特征包括要印刷的双镶嵌图案。 压印模具与沉积在转移层上的可光聚合的有机硅成像层接触，转移层被旋涂或以其它方式沉积在基底的电介质层上。 当可光聚合层暴露于照明源时，它可以用匹配印模的双镶嵌图案的结构固化。 卤素穿透蚀刻随后氧传递蚀刻将通孔从成像层转移到转移层中。 第二个卤素穿透蚀刻，随后是第二次氧转移蚀刻，将沟槽从成像层转移到转移层中。 电介质蚀刻将图案从转印层转移到电介质层中。 然后，金属填充过程用金属填充介电层的双镶嵌开口。

    Selective epitaxial growth for tunable channel thickness
    39.
    发明授权
    Selective epitaxial growth for tunable channel thickness 有权
    选择性外延生长可调谐通道厚度

    公开(公告)号：US07105399B1

    公开(公告)日：2006-09-12

    申请号：US11004951

    申请日：2004-12-07

    申请人： Srikanteswara Dakshina-Murthy ,  Douglas Bonser ,  Hans Van Meer ,  David Brown

    发明人： Srikanteswara Dakshina-Murthy ,  Douglas Bonser ,  Hans Van Meer ,  David Brown

    IPC分类号： H01L21/302 ,  H01L21/8238

    CPC分类号： H01L27/1203 ,  H01L21/823807 ,  H01L21/84

    摘要： Gate electrodes with selectively tuned channel thicknesses are formed by selective epitaxial growth. Embodiments include forming shallow trench isolation regions in an SOI substrate, selectively removing the nitride stop layer and pad oxide layer in an exposed particular active region, and implementing selective epitaxial growth to increase the thickness of the semiconductor layer in the particular active region. Subsequently, the remaining nitride stop and pad oxide layers in other active regions are removed, gate dielectric layers formed, as by thermal oxidation, and the transistors completed.

    摘要翻译： 通过选择性外延生长形成具有选择性调谐的沟道厚度的栅极。 实施例包括在SOI衬底中形成浅沟槽隔离区域，选择性地去除暴露的特定有源区域中的氮化物阻挡层和衬垫氧化物层，以及实现选择性外延生长以增加特定有源区域中的半导体层的厚度。 随后，去除其它有源区中剩余的氮化物阻挡层和焊盘氧化物层，如通过热氧化形成栅介电层，并完成晶体管。

    Method for reducing resist height erosion in a gate etch process
    40.
    发明授权
    Method for reducing resist height erosion in a gate etch process 有权
    在栅极蚀刻工艺中降低抗蚀剂高度腐蚀的方法

    公开(公告)号：US07005386B1

    公开(公告)日：2006-02-28

    申请号：US10656467

    申请日：2003-09-05

    申请人： Scott Bell ,  Srikanteswara Dakshina-Murthy ,  Chih-Yuh Yang ,  Ashok M. Khathuria

    发明人： Scott Bell ,  Srikanteswara Dakshina-Murthy ,  Chih-Yuh Yang ,  Ashok M. Khathuria

    IPC分类号： H01L21/302

    CPC分类号： H01L21/32139 ,  H01L21/0274 ,  H01L21/31058

    摘要： According to one exemplary embodiment, a method for reducing resist height erosion in a gate etch process comprises a step of forming a first resist mask on an anti-reflective coating layer situated over a substrate, where the first resist mask has a first width. The anti-reflective coating layer may be, for example, an organic material. The method further comprises a step of trimming the first resist mask to form a second resist mask, where the second resist mask has a second width, and where the second width is less than the first width. The step of trimming the first resist mask may further comprise, for example, etching the anti-reflective coating layer. According to this exemplary embodiment, the method further comprises a step of performing an HBr plasma treatment on the second resist mask, wherein the HBr plasma treatment causes a vertical etch rate of the second resist mask to decrease.

    摘要翻译： 根据一个示例性实施例，用于降低栅极蚀刻工艺中的抗蚀剂高度腐蚀的方法包括在位于衬底上的抗反射涂层上形成第一抗蚀剂掩模的步骤，其中第一抗蚀剂掩模具有第一宽度。 抗反射涂层可以是例如有机材料。 该方法还包括修整第一抗蚀剂掩模以形成第二抗蚀剂掩模的步骤，其中第二抗蚀剂掩模具有第二宽度，并且其中第二宽度小于第一宽度。 修整第一抗蚀剂掩模的步骤还可以包括例如蚀刻抗反射涂层。 根据该示例性实施例，该方法还包括在第二抗蚀剂掩模上执行HBr等离子体处理的步骤，其中HBr等离子体处理导致第二抗蚀剂掩模的垂直蚀刻速率降低。