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    PROCESS FOR ZIPRASIDONE USING NOVEL INTERMEDIATES
    31.
    发明申请
    PROCESS FOR ZIPRASIDONE USING NOVEL INTERMEDIATES 审中-公开
    使用新的中间体的ZIPRASIDONE的方法

    公开(公告)号：US20090163513A1

    公开(公告)日：2009-06-25

    申请号：US10596675

    申请日：2005-01-27

    Applicant: Bandi Parthasaradhi Reddy ,  Kura Rathnakar Reddy ,  Rapolu Raji Reddy ,  Dasari Muralidhara Reddy ,  Itiyala Srinivas Reddy

    Inventor： Bandi Parthasaradhi Reddy ,  Kura Rathnakar Reddy ,  Rapolu Raji Reddy ,  Dasari Muralidhara Reddy ,  Itiyala Srinivas Reddy

    IPC: A61K31/501 ,  C07D417/14 ,  C07F7/10

    CPC classification number: C07F7/10 ,  C07D417/12

    Abstract: The present invention relates to a novel process for the preparation of high purity ziprasidone and pharmaceutically acceptable acid addition salts of ziprasidone; and solvates and hydrates thereof using novel intermediates and a purification method for ziprasidone and pharmaceutically acceptable acid addition salts of ziprasidone; and solvates and hydrates thereof.Thus, 1-(1,2-benzisothiazol-3-yl)piperazine is silylated with trimethylsilylchloride in methylene chloride in the presence of triethylamine and the solvent is distilled off to obtain silylated 1-(1,2-benzisothiazol-3-yl)piperazine. The silylated compound is reacted with 5-(2-chloroethyl)-6-chloro-oxindole in the presence of sodium carbonate to obtain ziprasidone.

    Abstract translation: 本发明涉及一种制备齐拉西酮的高纯度齐拉西酮和药学上可接受的酸加成盐的新方法; 并使用新的中间体和齐拉西酮和齐拉西酮的药学上可接受的酸加成盐的纯化方法进行溶剂化和水合; 并且其溶剂合物和水合物。 因此，在三乙基胺存在下，将1-（1,2-苯并异噻唑-3-基）哌嗪甲硅烷基化，在二氯甲烷中，蒸出溶剂，得到甲硅烷基化的1-（1,2-苯并异噻唑-3-基） 哌嗪。 甲硅烷基化化合物在碳酸钠存在下与5-（2-氯乙基）-6-氯 - 羟吲哚反应，得到齐拉西酮。

    Tristate structures for programmable logic devices
    35.
    发明授权
    Tristate structures for programmable logic devices 失效
    可编程逻辑器件的三态结构

    公开(公告)号：US06882177B1

    公开(公告)日：2005-04-19

    申请号：US09832685

    申请日：2001-04-10

    Applicant: Srinivas Reddy ,  Richard G. Cliff

    Inventor： Srinivas Reddy ,  Richard G. Cliff

    IPC: H03K19/177 ,  G06F7/38

    CPC classification number: H03K19/17752 ,  H03K19/17728 ,  H03K19/17736

    Abstract: A programmable logic device architecture including tristate structures. The programmable logic device architecture provides tristate structures which may be logically or programmably controlled, or both. Through these tristate structures, the logic elements may be coupled to the programmable interconnect, where they may be coupled with other logic elements of the programmable logic device. Using these tristate structures, the signal pathways of the architecture may be dynamically reconfigured.

    Abstract translation: 包括三态结构的可编程逻辑器件架构。 可编程逻辑器件架构提供了可逻辑地或可编程地控制的三态结构，或两者。 通过这些三态结构，逻辑元件可以耦合到可编程互连，其中它们可以与可编程逻辑器件的其它逻辑元件耦合。 使用这些三态结构，可以动态地重新配置架构的信号路径。

    Programmable logic device incorporating and input/output overflow bus
    37.
    发明授权
    Programmable logic device incorporating and input/output overflow bus 失效
    可编程逻辑器件并入和输入/输出溢出总线

    公开(公告)号：US6094064A

    公开(公告)日：2000-07-25

    申请号：US121250

    申请日：1998-07-23

    Applicant: Manuel Mejia ,  David Jefferson ,  Srinivas Reddy

    Inventor： Manuel Mejia ,  David Jefferson ,  Srinivas Reddy

    IPC: H03K19/173 ,  H03K19/177

    CPC classification number: H03K19/17744 ,  H03K19/1736

    Abstract: A programmable logic device architecture incorporating a peripheral overflow bus is disclosed. In a preferred embodiment, the programmable logic device has a core region that includes at least a plurality of logic cells interconnected by way of associated programmable logic cell conductors. The interconnected logic cells form an array suitable for use in implementing desired logic functions. The programmable logic device also has a peripheral region. The peripheral region includes at least a plurality of bi-directional ports of which selected ones may be coupled to external circuitry. The peripheral region also includes a bi-directional peripheral I/O overflow bus suitably arranged to pass a plurality of control signals and a plurality of data signals between the core region and the plurality of bi-directional ports.

    Abstract translation: 公开了一种结合外设溢出总线的可编程逻辑器件架构。 在优选实施例中，可编程逻辑器件具有核心区域，其包括通过相关联的可编程逻辑单元导体互连的至少多个逻辑单元。 互连的逻辑单元形成适合用于实现期望的逻辑功能的阵列。 可编程逻辑器件还具有外围区域。 外围区域包括至少多个双向端口，其中所选择的端口可以耦合到外部电路。 外围区域还包括适当地布置成在核心区域和多个双向端口之间传递多个控制信号和多个数据信号的双向外围I / O溢出总线。

    Energy absorbing occupant restraint system
    38.
    发明授权
    Energy absorbing occupant restraint system 有权
    吸能乘员约束系统

    公开(公告)号：US6056320A

    公开(公告)日：2000-05-02

    申请号：US178119

    申请日：1998-10-23

    Applicant: Mustafa A. Khalifa ,  Kenneth Budowick ,  Srinivas Reddy Malapati ,  John P. Paris ,  Oscar H. Sharp

    Inventor： Mustafa A. Khalifa ,  Kenneth Budowick ,  Srinivas Reddy Malapati ,  John P. Paris ,  Oscar H. Sharp

    IPC: B60R22/22 ,  B60R22/28

    CPC classification number: B60R22/28 ,  B60R22/22

    Abstract: An energy absorbing occupant restraint system for a motor vehicle includes a load-limiting buckle assembly. The buckle assembly includes a first elongated member adapted to be secured to the floor of the motor vehicle and a second elongated member. The buckle assembly further includes a buckle attached to the first elongated member. The buckle is adapted to releasably engage a tongue assembly carried by a seat belt webbing. A connector member interconnects the first and second elongated members. The second elongated member is configured so as to incrementally allow the second elongated member to translate relative to the first elongated member when the first elongated member is acted upon by a load which exceeds a predetermined level. In the preferred embodiment, the second elongated member is a sleeve member which telescopically receives the first elongated member. The sleeve member has an elongated aperture with a plurality of deflectable tangs which resist deflection until acted upon by a predetermined load.

    Abstract translation: 用于机动车辆的能量吸收乘员约束系统包括负载限制带扣组件。 带扣组件包括适于固定到机动车辆的地板上的第一细长构件和第二细长构件。 带扣组件还包括附接到第一细长构件的带扣。 带扣适于可释放地接合由安全带织带携带的舌组件。 连接器构件将第一和第二细长构件互连。 第二细长构件被构造成当第一细长构件被超过预定水平的负载作用时，第二细长构件相对于第一细长构件递增地允许平移。 在优选实施例中，第二细长构件是可伸缩地容纳第一细长构件的套筒构件。 套筒构件具有细长的孔，其具有多个可偏转的柄脚，其抵抗偏转直到被预定的负载作用。

    System for distributing clocks using a delay lock loop in a programmable logic circuit
    39.
    发明授权
    System for distributing clocks using a delay lock loop in a programmable logic circuit 失效
    用于在可编程逻辑电路中使用延迟锁定环路分配时钟的系统

    公开(公告)号：US5963069A

    公开(公告)日：1999-10-05

    申请号：US971315

    申请日：1997-11-17

    Applicant: David E. Jefferson ,  L. Todd Cope ,  Srinivas Reddy ,  Richard G. Cliff

    Inventor： David E. Jefferson ,  L. Todd Cope ,  Srinivas Reddy ,  Richard G. Cliff

    IPC: G06F1/10 ,  H03K19/177 ,  H03L7/081 ,  H03L7/087 ,  H03L7/08

    CPC classification number: H03K19/1774 ,  G06F1/10 ,  H03K19/17732 ,  H03L7/0814 ,  H03L7/087

    Abstract: A system (100) for distributing a clock signal to many points on an integrated circuit. The system includes using a delay lock loop with specific digital circuits to accomplish the phase error detection and delay element selection. In one embodiment, two flip-flops are used to detect a phase error. In another embodiment, both macro (202) and micro phase detectors (218) are used and the delay element selection is performed in two stages by using a shift register (210) in a first stage and a counter (220) in a second stage. Another feature of the present invention is, the ability to distribute the reference clock or a synchronized clock to different portions of the circuitry on an integrated circuit. Multiple clock distribution systems are provided which may be selected.

    Abstract translation: 一种用于将时钟信号分配给集成电路上的许多点的系统（100）。 该系统包括使用具有特定数字电路的延迟锁定环来完成相位误差检测和延迟元件选择。 在一个实施例中，使用两个触发器来检测相位误差。 在另一个实施例中，使用宏（202）和微相位检测器（218），并且通过使用第一级中的移位寄存器（210）和在第二级中的计数器（220），两级执行延迟元件选择 。 本发明的另一个特征是将参考时钟或同步时钟分配到集成电路上的电路的不同部分的能力。 提供可选择的多个时钟分配系统。

    Hierarchical interconnect for programmable logic devices
    40.
    发明授权
    Hierarchical interconnect for programmable logic devices 失效
    可编程逻辑器件的分层互连

    公开(公告)号：US5883526A

    公开(公告)日：1999-03-16

    申请号：US840113

    申请日：1997-04-17

    Applicant: Srinivas Reddy ,  Manuel Mejia

    Inventor： Srinivas Reddy ,  Manuel Mejia

    IPC: H03K19/177

    CPC classification number: H03K19/17736 ,  H03K19/17704 ,  H03K19/17796

    Abstract: A hierarchical interconnect structure between logic elements, logic array blocks and global interconnects in a programmable logic device is disclosed. The present invention provides a first group of local interconnect lines that couple to outputs of more than one logic element in a block, and a second group of local interconnect lines that are divided into independent segments coupled to a subset of the logic elements in a block. By eliminating the one-to-one correspondence between the number of logic elements in a logic array block and the number of local interconnect wires, the present invention makes possible the inclusion of more logic element in one block in an area efficient manner.

    Abstract translation: 公开了可编程逻辑器件中的逻辑元件，逻辑阵列块和全局互连之间的分层互连结构。 本发明提供了耦合到块中多于一个逻辑元件的输出的第一组局部互连线，以及第二组局部互连线，其被划分为耦合到块中的逻辑元件的子集的独立段 。 通过消除逻辑阵列块中的逻辑元件的数量与局部互连线的数量之间的一一对应关系，本发明使得可以以区域有效的方式在一个块中包含更多的逻辑元件。

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