公开(公告)号：US08610460B2

公开(公告)日：2013-12-17

申请号：US13590885

申请日：2012-08-21

Applicant: Tae Jin Kang

Inventor： Tae Jin Kang

IPC: H03K17/16 ,  H03K19/003 ,  G11C5/14 ,  G11C7/10

CPC classification number: G11C7/1045 ,  G11C7/1057 ,  G11C7/1084

Abstract: Semiconductor modules are provided. The semiconductor module includes a first semiconductor chip configured for storing an information signal that is set in response to a command/address signal and which determines reception of an on-die termination (ODT) signal in a power down mode in response to the information signal to control activation of a first ODT circuit; and a second semiconductor chip configured for sharing and utilizing the first ODT circuit included in the first semiconductor chip.

Abstract translation: 提供半导体模块。 半导体模块包括：第一半导体芯片，被配置为存储响应于命令/地址信号设置的信息信号，并且响应于信息信号确定在断电模式下接收片上终端（ODT）信号 以控制第一ODT电路的激活; 以及配置为共享和利用包括在第一半导体芯片中的第一ODT电路的第二半导体芯片。

公开(公告)号：US20130114347A1

公开(公告)日：2013-05-09

申请号：US13336876

申请日：2011-12-23

Applicant: Tae Jin KANG

Inventor： Tae Jin KANG

IPC: G11C7/10 ,  G11C7/00 ,  G11C29/00

CPC classification number: G11C29/56008 ,  G11C29/56012

Abstract: A semiconductor system includes a semiconductor memory device configured to, during a test mode, store received data in a memory cell in response to a write command, read the stored data as information data in response to a read command, and internally store the information data, in response to the read command, in synchronization with a pulse generated when a level of the information data changes.

Abstract translation: 半导体系统包括：半导体存储器件，被配置为在测试模式期间响应于写入命令将接收到的数据存储在存储器单元中，响应于读取命令读取存储的数据作为信息数据，并在内部存储信息数据 响应于读取命令，与信息数据的级别变化时产生的脉冲同步。

公开(公告)号：US20120113728A1

公开(公告)日：2012-05-10

申请号：US13096669

申请日：2011-04-28

Applicant: Kyoung Hwan KWON ,  Tae Jin KANG ,  Sang Kwon LEE

Inventor： Kyoung Hwan KWON ,  Tae Jin KANG ,  Sang Kwon LEE

IPC: G11C7/10 ,  G11C8/18

CPC classification number: G11C7/1072 ,  G11C7/1006 ,  G11C7/1087 ,  G11C7/1093 ,  G11C7/1096 ,  G11C7/222

Abstract: A data input circuit includes a clock sampling unit, a final clock generation unit, and a write latch signal generation unit. The sampling unit is configured to generate a shifting signal including a pulse generated after a write latency is elapsed, and generate a sampling clock by sampling an internal clock during a burst period from substantially a time when the pulse of the shifting signal is generated. The final clock generation unit is configured to generate a level signal by latching the shifting signal in synchronization with the sampling clock and generate a final clock from the level signal in response to a burst signal. The write latch signal generation unit is configured to generate an enable signal by latching the final clock and generate a write latch signal for latching and outputting aligned data in response to the enable signal.

Abstract translation: 数据输入电路包括时钟采样单元，最终时钟产生单元和写入锁存信号产生单元。 采样单元被配置为产生包括在写入等待时间之后产生的脉冲的移位信号，并且在从产生移位信号的脉冲的时间开始的脉冲串周期期间，通过对内部时钟进行采样来产生采样时钟。 最终时钟生成单元被配置为通过与采样时钟同步地锁存移位信号来产生电平信号，并且响应于突发信号从电平信号产生最终时钟。 写锁存信号生成单元被配置为通过锁存最终时钟来产生使能信号，并且响应于使能信号产生用于锁存和输出对准数据的写锁存信号。

公开(公告)号：US20110171015A1

公开(公告)日：2011-07-14

申请号：US12967523

申请日：2010-12-14

Applicant: Tae Jin KANG

Inventor： Tae Jin KANG

IPC: F01D13/00 ,  B23P15/00

CPC classification number: F04D29/051 ,  F04D17/105 ,  F04D17/122 ,  F04D29/4206 ,  Y10T29/49243

Abstract: Provided is a centrifugal compressor. In the centrifugal compressor, a plurality of sub-compressors each of which includes an impeller are connected in parallel to increase a compression capacity, the plurality of sub-compressors are each assembled to a single common shaft that is rotated by a driving unit, and the impellers of the plurality of sub-compressors are disposed in opposing directions. The centrifugal compressor reduces a production cost, and cancels thrusts during driving so as to reduce a loss of a bearing, thereby increasing efficiency of the compressor.

Abstract translation: 提供了一种离心式压缩机。 在离心式压缩机中，并联连接多个分别包括叶轮的副压缩机以提高压缩容量，多个副压缩机各自组装成由驱动单元旋转的单个公共轴，并且 多个副压缩机的叶轮相对设置。 离心式压缩机降低了生产成本，并且消除了驱动过程中的推力，从而减少了轴承的损失，从而提高了压缩机的效率。

公开(公告)号：US20100135098A1

公开(公告)日：2010-06-03

申请号：US12459345

申请日：2009-06-30

Applicant: Tae Jin Kang

Inventor： Tae Jin Kang

IPC: G11C5/14 ,  G11C7/00 ,  G11C8/18 ,  G11C7/10

CPC classification number: G11C5/147 ,  G11C11/4074 ,  G11C11/4076 ,  G11C2207/2227

Abstract: A semiconductor memory device comprises a power control circuit for outputting a power voltage in a read operation period and a write operation period, and an internal circuit operating by the power voltage supplied thereto.

Abstract translation: 半导体存储器件包括用于在读操作期间和写操作期间输出电源电压的电源控制电路，以及由供给的电源电压进行工作的内部电路。

公开(公告)号：US20080144422A1

公开(公告)日：2008-06-19

申请号：US12071741

申请日：2008-02-26

Applicant: Tae-Jin Kang ,  Bong-Hwa Jeong

Inventor： Tae-Jin Kang ,  Bong-Hwa Jeong

IPC: G11C8/00

CPC classification number: G11C7/1051 ,  G11C7/1057 ,  G11C7/1066 ,  G11C7/1072 ,  G11C7/22 ,  G11C7/222

Abstract: An data output circuit for outputting a data stored in a core of a semiconductor memory device includes a clock generator for generating a rising clock and a falling clock by using an external clock, a clock repeater for outputting the rising clock and the falling clock as one of a high voltage clock and a low voltage clock in response to an external voltage level check signal, a level shifter for outputting a high voltage data generated by shifting the data synchronized with the high voltage clock, a data carrier for outputting a low voltage data synchronized with the low voltage clock, and a data repeater for outputting one of the high voltage data and the low voltage data in response to the external voltage level check signal.

Abstract translation: 用于输出存储在半导体存储器件的核心中的数据的数据输出电路包括用于通过使用外部时钟产生上升时钟和下降时钟的时钟发生器，用于输出上升时钟和下降时钟的时钟转发器 响应于外部电压电平检查信号的高压时钟和低电压时钟;电平移位器，用于输出通过移位与高电压时钟同步的数据产生的高电压数据;数据载体，用于输出低电压数据 与低电压时钟同步;以及数据中继器，用于响应于外部电压电平检查信号输出高电压数据和低电压数据中的一个。

公开(公告)号：US07142022B2

公开(公告)日：2006-11-28

申请号：US10739232

申请日：2003-12-18

Applicant: Tae Jin Kang ,  Kee Teok Park

Inventor： Tae Jin Kang ,  Kee Teok Park

IPC: G01R19/00

CPC classification number: G11C7/225 ,  G11C7/22 ,  H03K5/2481 ,  H03K19/0016 ,  H03K19/018528

Abstract: A clock enable buffer for entry of a self-refresh mode. The clock enable buffer includes a current mirror load connected between a voltage source and first and second nodes, wherein the current mirror load has first and second transistors; a third transistor connected between the first node and a third node, wherein the third transistor is turned on according to a reference voltage; a fourth transistor connected between the second node and the third node, for controlling the current mirror load in response to a clock enable signal; a fifth transistor connected between the third node and a ground, wherein the fifth transistor is turned on according to a self-refresh signal; and a sixth transistor that is turned on according to an inverted self-refresh signal to make the potential of the first node a Low level.

Abstract translation: 用于输入自刷新模式的时钟使能缓冲器。 所述时钟使能缓冲器包括连接在电压源和第一和第二节点之间的电流镜像负载，其中电流反射镜负载具有第一和第二晶体管; 连接在所述第一节点和第三节点之间的第三晶体管，其中所述第三晶体管根据参考电压导通; 连接在第二节点和第三节点之间的第四晶体管，用于响应于时钟使能信号控制电流镜像负载; 连接在所述第三节点和地之间的第五晶体管，其中所述第五晶体管根据自刷新信号导通; 以及根据反相自刷新信号导通的第六晶体管，以使第一节点的电位为低电平。

公开(公告)号：US20060140044A1

公开(公告)日：2006-06-29

申请号：US11077612

申请日：2005-03-11

Applicant: Tae-Jin Kang

Inventor： Tae-Jin Kang

IPC: G11C8/00

CPC classification number: G11C7/222 ,  G11C7/1051 ,  G11C7/1066 ,  G11C7/1072

Abstract: A clock signal generation apparatus for generating a reference clock signal for outputting data in synchronization with an external clock signal from a semiconductor memory device, including: a clock signal generation unit for receiving an internal clock signal to generate the reference clock signal according to a control signal; and a control unit for generating the control signal based on a read command, a write command and an external address.

公开(公告)号：US08896340B2

公开(公告)日：2014-11-25

申请号：US13615373

申请日：2012-09-13

Applicant: Tae Jin Kang

Inventor： Tae Jin Kang

IPC: H03K19/003

CPC classification number: H03K19/0005

Abstract: Semiconductor modules are provided. The semiconductor module includes semiconductor chips with one or more ranks. The semiconductor module includes a mode register configured for storing a first information signal whose logic level is set or determined according to a number of the ranks and an on-die termination (ODT) controller configured for generating an internal control signal for activating an ODT circuit in response to the first information signal. The internal control signal is enabled during a read operation or disabled during a write operation.

Abstract translation: 提供半导体模块。 半导体模块包括具有一个或多个等级的半导体芯片。 半导体模块包括模式寄存器，其被配置为存储根据等级的数量来设置或确定其逻辑电平的第一信息信号，以及配置用于生成用于激活ODT电路的内部控制信号的片上终端（ODT）控制器 响应于第一信息信号。 内部控制信号在读操作期间被使能，或者在写操作期间被禁止。

公开(公告)号：US08699279B2

公开(公告)日：2014-04-15

申请号：US13336876

申请日：2011-12-23

Applicant: Tae Jin Kang

Inventor： Tae Jin Kang

IPC: G11C7/10

CPC classification number: G11C29/56008 ,  G11C29/56012

Abstract: A semiconductor system includes a semiconductor memory device configured to, during a test mode, store received data in a memory cell in response to a write command, read the stored data as information data in response to a read command, and internally store the information data, in response to the read command, in synchronization with a pulse generated when a level of the information data changes.

Abstract translation: 半导体系统包括：半导体存储器件，被配置为在测试模式期间响应于写入命令将接收到的数据存储在存储器单元中，响应于读取命令读取存储的数据作为信息数据，并在内部存储信息数据 响应于读取命令，与信息数据的级别变化时产生的脉冲同步。