公开(公告)号：US07712009B2

公开(公告)日：2010-05-04

申请号：US11533169

申请日：2006-09-19

申请人： Masafumi Ito ,  Tomoaki Atsumi

发明人： Masafumi Ito ,  Tomoaki Atsumi

IPC分类号： H03M13/00

CPC分类号： H03M13/09 ,  H04B1/10

摘要： An object of the present invention is to provide a CRC circuit with more simple structure and low power consumption. The CRC circuit includes a first shift register to a p-th shift register, a first EXOR to a (p−1)th EXOR, and a switching circuit. A data signal, a select signal, and an output of a last stage of the p-th shift register are inputted to the switching circuit, and the switching circuit switches a first signal or a second signal in response to the select signal to be outputted.

摘要翻译： 本发明的目的是提供一种具有更简单的结构和低功耗的CRC电路。 CRC电路包括到第p移位寄存器的第一移位寄存器，第一EXOR到第（p-1）个EXOR和开关电路。 数据信号，选择信号和第p移位寄存器的最后级的输出被输入到开关电路，并且开关电路响应于要输出的选择信号而切换第一信号或第二信号 。

公开(公告)号：US20100079179A1

公开(公告)日：2010-04-01

申请号：US12568378

申请日：2009-09-28

申请人： Tomoaki Atsumi

发明人： Tomoaki Atsumi

IPC分类号： H03K21/00

CPC分类号： H03K23/52 ,  H04L7/007 ,  H04L7/0331 ,  H04L7/04

摘要： It is an object of the present invention to provide a semiconductor device that has a simple circuit structure, a small scale, and low power consumption, and can generate a desired clock signal. The semiconductor device has a clock generation circuit which generates a clock signal by dividing a modulated carrier wave, a divider circuit which generates a first divided signal by dividing a carrier wave, and a correction circuit which generates a second divided signal by further dividing the first divided signal, and has a function of performing correction for inverting the second divided signal in a period corresponding to a half period of the clock signal during modulation of the carrier wave and selecting whether the correction is performed or not.

摘要翻译： 本发明的目的是提供一种具有简单的电路结构，小规模和低功耗的半导体器件，并且可以产生期望的时钟信号。 半导体器件具有时钟生成电路，其通过分压调制后的载波产生时钟信号，分频电路通过划分载波产生第一分频信号;校正电路，其通过进一步分割第一分频信号产生第二分频信号 并且具有在对载波的调制期间对应于时钟信号的半周期的周期内执行用于反转第二分频信号的校正的功能，并且选择是否执行校正。

公开(公告)号：US07675512B2

公开(公告)日：2010-03-09

申请号：US10890110

申请日：2004-07-14

申请人： Jun Koyama ,  Tomoaki Atsumi

发明人： Jun Koyama ,  Tomoaki Atsumi

IPC分类号： G09G5/00

CPC分类号： G11C8/08 ,  G11C11/4085 ,  G11C11/418

摘要： A memory circuit using a thin film transistor has been problems such as the drop in yield and the decrease in speed of response of the memory circuit due to variations in transistors. The purpose of the invention is to improve the yield and speed of the response of a memory cell by driving a word line by a voltage which is different from the logical amplitude of the memory cell. The invention is applicable to an SRAM, a DRAM, a mask ROM, and the like. A memory circuit of the invention is formed integrally with a display device for realizing a multi-functional display device.

摘要翻译： 使用薄膜晶体管的存储器电路已经是由于晶体管的变化而导致的存储电路的产量下降和响应速度降低的问题。 本发明的目的是通过与存储单元的逻辑振幅不同的电压驱动字线来提高存储单元的响应的产量和速度。 本发明可应用于SRAM，DRAM，掩模ROM等。 本发明的存储电路与用于实现多功能显示装置的显示装置一体地形成。

公开(公告)号：US20080164478A1

公开(公告)日：2008-07-10

申请号：US11957641

申请日：2007-12-17

申请人： Satoshi Murakami ,  Yosuke Tsukamoto ,  Tomoaki Atsumi ,  Masayuki Sakakura

发明人： Satoshi Murakami ,  Yosuke Tsukamoto ,  Tomoaki Atsumi ,  Masayuki Sakakura

IPC分类号： H01L27/12

CPC分类号： H01L29/04 ,  G02F1/13454 ,  G02F1/136204 ,  H01L27/12 ,  H01L27/1214 ,  H01L27/124

摘要： In manufacturing a semiconductor device, static electricity is generated while contact holes are formed in an interlayer insulating film by dry etching. Damage to a pixel region or a driving circuit region due to travel of the static electricity generated is prevented. Gate signal lines are spaced apart from each other above a crystalline semiconductor film. Therefore a first protective circuit is not electrically connected when contact holes are opened in an interlayer insulating film. The static electricity generated during dry etching for opening the contact holes moves from the gate signal line, damages a gate insulating film, passes the crystalline semiconductor film, and again damages the gate insulating film before it reaches the gate signal line. As the static electricity generated during the dry etching damages the first protective circuit, the energy of the static electricity is reduced until it loses the capacity of damaging a driving circuit TFT. The driving circuit TFT is thus prevented from suffering electrostatic discharge damage.

摘要翻译： 在制造半导体器件时，通过干蚀刻在层间绝缘膜中形成接触孔时产生静电。 防止了由于所产生的静电的行进而对像素区域或驱动电路区域的损害。 栅极信号线在结晶半导体膜之上彼此间隔开。 因此，当在层间绝缘膜中打开接触孔时，第一保护电路不电连接。 在干蚀刻期间产生的用于打开接触孔的静电从栅极信号线移动，损坏栅极绝缘膜，通过晶体半导体膜，并且在栅极绝缘膜到达栅极信号线之前再次损坏栅极绝缘膜。 由于在干蚀刻期间产生的静电损害第一保护电路，所以静电的能量减小，直到损失驱动电路TFT的能力。 从而防止了驱动电路TFT遭受静电放电损坏。

公开(公告)号：US20080153450A1

公开(公告)日：2008-06-26

申请号：US12003354

申请日：2007-12-21

申请人： Tomoaki Atsumi ,  Hidetomo Kobayashi

发明人： Tomoaki Atsumi ,  Hidetomo Kobayashi

IPC分类号： H04B1/16

CPC分类号： G06K19/0723 ,  G06K19/0702 ,  G06K19/07786 ,  H04B5/0062

摘要： A demodulation signal is generated by provision of a demodulation signal generation circuit to the semiconductor device capable of wireless communication and by obtainment of a difference between voltages having opposite polarities by the demodulation signal generation circuit. Alternatively, a plurality of demodulation signal generation circuits and a selective circuit which selects a demodulation signal generation circuit depending on characteristics of a received signal are provided, where operation of a second demodulation signal generation circuit stops when a first demodulation signal generation circuit is operated. The selective circuit includes an inverter circuit, a flip-flop circuit, and a selector circuit. When the second demodulation signal generation circuit has a comparator and the like, power consumption thereof is reduced.

摘要翻译： 通过向能够进行无线通信的半导体装置提供解调信号生成电路，并且通过解调信号生成电路获得具有相反极性的电压之间的差异来生成解调信号。 或者，提供多个解调信号生成电路和根据接收信号的特性来选择解调信号生成电路的选择电路，其中当第一解调信号产生电路被操作时第二解调信号产生电路的操作停止。 选择电路包括反相器电路，触发器电路和选择器电路。 当第二解调信号发生电路具有比较器等时，其功耗降低。

公开(公告)号：US07324097B2

公开(公告)日：2008-01-29

申请号：US10833862

申请日：2004-04-28

申请人： Jun Koyama ,  Munehiro Azami ,  Yutaka Shionoiri ,  Tomoaki Atsumi

发明人： Jun Koyama ,  Munehiro Azami ,  Yutaka Shionoiri ,  Tomoaki Atsumi

IPC分类号： G09G5/00

CPC分类号： H03K19/018578 ,  G09G3/3208 ,  G09G3/3225 ,  G09G3/3685 ,  G09G2310/0289 ,  G09G2310/0291

摘要： A level shifter that accommodates lower driving voltage of a driver circuit and has a sufficient capability of converting the amplitude of an input signal even when the voltage amplitude of the input signal is low is provided. A level shifter utilizing a current mirror circuit 150 and a differential circuit 160 is used in a portion for converting the voltage amplitude of the signal. Since the potential difference of a signal input through transistors 105 and 106 to the differential circuit 120 is amplified and outputted, the voltage amplitude can be normally converted without influence of the threshold of a transistor even when the voltage amplitude of the input signal is low.

摘要翻译： 提供了一种电平移位器，其适应驱动电路的较低驱动电压，并且即使当输入信号的电压幅度低时也具有足够的转换输入信号的幅度的能力。 在用于转换信号的电压幅度的部分中使用利用电流镜电路150和差分电路160的电平移位器。 由于通过晶体管105和106输入到差分电路120的信号的电位差被放大并输出，所以即使当输入信号的电压幅度低时，也可以不影响晶体管的阈值而正常地转换电压幅度。

公开(公告)号：US20070099400A1

公开(公告)日：2007-05-03

申请号：US11607021

申请日：2006-12-01

申请人： Kiyoshi Kato ,  Tomoaki Atsumi ,  Atsuo Isobe

发明人： Kiyoshi Kato ,  Tomoaki Atsumi ,  Atsuo Isobe

IPC分类号： H01L21/20 ,  H01L21/36

CPC分类号： H01L21/02678 ,  H01L21/02683 ,  H01L21/2026 ,  H01L27/12 ,  H01L27/1281 ,  H01L29/66757 ,  H01L29/78675 ,  H01L29/78696

摘要： According to the invention, a plurality of semiconductor devices which are required to have conformance are formed from crystalline semiconductor films having uniform crystallinity on the same line, and a semiconductor circuit in which variation between semiconductor devices is small can be provided, and a semiconductor integrated circuit having high conformance can be provided. The invention is characterized in that, in a part or whole of thin film transistors which configure an analog circuit such as a current mirror circuit, a differential amplifier circuit, or an operational amplifier, in which high conformance is required for semiconductor devices included therein, channel forming regions have crystalline semiconductor films on the same line. High conformance can be expected for an analog circuit which has the crystalline semiconductor films on the same line formed using the invention as the channel forming regions of the thin film transistors. That is, the invention is characterized in that, among the thin film transistors which configures the analog circuit, the channel forming regions of the thin film transistors having at least the same polarity are formed on the same line.

摘要翻译： 根据本发明，需要具有一致性的多个半导体器件由同一直线上具有均匀结晶度的晶体半导体膜形成，并且可以提供其中半导体器件之间的变化小的半导体电路，以及半导体集成 可以提供具有高一致性的电路。 本发明的特征在于，在其中包括其中的半导体器件需要高一致性的诸如电流镜电路，差分放大器电路或运算放大器的模拟电路的一部分或全部中， 通道形成区域在同一行上具有结晶半导体膜。 对于具有使用本发明形成的同一线上的晶体半导体膜作为薄膜晶体管的沟道形成区域的模拟电路，可以期待高度一致性。 也就是说，本发明的特征在于，在构成模拟电路的薄膜晶体管中，在同一线上形成具有至少相同极性的薄膜晶体管的沟道形成区域。

公开(公告)号：US07184014B2

公开(公告)日：2007-02-27

申请号：US09969591

申请日：2001-10-04

申请人： Jun Koyama ,  Tomoaki Atsumi ,  Hiroyuki Miyake

发明人： Jun Koyama ,  Tomoaki Atsumi ,  Hiroyuki Miyake

IPC分类号： G09G3/36

CPC分类号： G09G3/3648 ,  G09G3/3677 ,  G09G3/3688 ,  G09G2300/0809 ,  G09G2300/0828 ,  G09G2300/0842 ,  G09G2300/0857

摘要： A liquid crystal display device with low power consumption is provided. In the liquid crystal display device having a source signal line driver circuit, a gate signal line driver circuit, a DAC controller, and a pixel portion and performing an image display using an n-bit (n is a natural number, n≧2) digital image signal, one pixel has memory circuits for storing an n-bit digital image signal and a D/A converter, and the n-bit digital image signal for one frame can be stored in the pixel. In case of a static image display, the image signal stored in the memory circuits is read out every frame to perform the display, and thus, only a DAC controller is driven during the display. Therefore, this contributes to a reduction of the power consumption of the entire liquid crystal display device.

摘要翻译： 提供具有低功耗的液晶显示装置。 在具有源极信号线驱动电路，栅极信号线驱动电路，DAC控制器和像素部分的液晶显示装置中，使用n位（n为自然数，n> = 2）进行图像显示 ）数字图像信号，一个像素具有用于存储n位数字图像信号和D / A转换器的存储电路，并且用于一帧的n位数字图像信号可以存储在像素中。 在静态图像显示的情况下，每帧读出存储在存储器电路中的图像信号以进行显示，因此在显示期间仅驱动DAC控制器。 因此，这有助于降低整个液晶显示装置的功耗。

公开(公告)号：US07158439B2

公开(公告)日：2007-01-02

申请号：US10890173

申请日：2004-07-14

申请人： Yutaka Shionoiri ,  Tomoaki Atsumi ,  Kiyoshi Kato

发明人： Yutaka Shionoiri ,  Tomoaki Atsumi ,  Kiyoshi Kato

IPC分类号： G11C8/00

CPC分类号： G11C7/1096 ,  G11C7/1078 ,  G11C7/12 ,  G11C11/4094 ,  G11C17/12

摘要： A memory having a bit line, a word line crossing the bit line, a memory cell electrically connected to the bit line and to the word line, a column decoder and a selector including a clocked inverter having a plurality of transistors electrically connected in series between a first power source and a second power source is provided. An input node of the clocked inverter is connected to the bit line, an output node of the clocked inverter is electrically connected to a data line, the plurality of transistors comprise a P-type transistor and a N-type transistor, a gate electrode of the P-type transistor and a gate electrode of the N-type transistor are electrically connected to the column decoder, and a sense amplifier is not interposed between the bit line and the input node of the clocked inverter.

摘要翻译： 具有位线的存储器，与位线交叉的字线，电连接到位线和字线的存储单元，列解码器和选择器，包括时钟反相器，其具有串联电连接的多个晶体管 提供第一电源和第二电源。 时钟反相器的输入节点连接到位线，时钟反相器的输出节点电连接到数据线，多个晶体管包括P型晶体管和N型晶体管，栅极电极 P型晶体管和N型晶体管的栅极电连接到列解码器，并且读出放大器不插入在时钟反相器的位线和输入节点之间。

公开(公告)号：US07145175B2

公开(公告)日：2006-12-05

申请号：US10934997

申请日：2004-09-07

申请人： Kiyoshi Kato ,  Tomoaki Atsumi ,  Atsuo Isobe

发明人： Kiyoshi Kato ,  Tomoaki Atsumi ,  Atsuo Isobe

IPC分类号： H01L29/04 ,  H01L31/06 ,  H01L31/376 ,  H01L31/20

CPC分类号： H01L21/02678 ,  H01L21/02683 ,  H01L21/2026 ,  H01L27/12 ,  H01L27/1281 ,  H01L29/66757 ,  H01L29/78675 ,  H01L29/78696

摘要： According to the invention, a plurality of semiconductor devices which are required to have conformance are formed from crystalline semiconductor films having uniform crystallinity on the same line, and a semiconductor circuit in which variation between semiconductor devices is small can be provided, and a semiconductor integrated circuit having high conformance can be provided. The invention is characterized in that, in a part or whole of thin film transistors which configure an analog circuit such as a current mirror circuit, a differential amplifier circuit, or an operational amplifier, in which high conformance is required for semiconductor devices included therein, channel forming regions have crystalline semiconductor films on the same line. High conformance can be expected for an analog circuit which has the crystalline semiconductor films on the same line formed using the invention as the channel forming regions of the thin film transistors. That is, the invention is characterized in that, among the thin film transistors which configures the analog circuit, the channel forming regions of the thin film transistors having at least the same polarity are formed on the same line.