公开(公告)号：US20060053258A1

公开(公告)日：2006-03-09

申请号：US10936952

申请日：2004-09-08

申请人： Yen-Cheng Liu ,  Krishnakanth Sistla ,  George Cai

发明人： Yen-Cheng Liu ,  Krishnakanth Sistla ,  George Cai

IPC分类号： G06F12/00

CPC分类号： G06F12/084 ,  G06F12/0811 ,  G06F12/0817 ,  G06F12/0831

摘要： A caching architecture within a microprocessor to filter core cache accesses. More particularly, embodiments of the invention relate to a technique to manage transactions, such as snoops, within a processor having a number of processor core caches and an inclusive shared cache.

摘要翻译： 微处理器内的缓存架构，用于过滤核心高速缓存访​​问。 更具体地，本发明的实施例涉及在具有多个处理器核心高速缓存和包含共享高速缓存的处理器内管理诸如窥探之类的事务的技术。

公开(公告)号：US20190171575A1

公开(公告)日：2019-06-06

申请号：US16264447

申请日：2019-01-31

申请人： Wei CHEN ,  Eswaramoorthi NALLUSAMY ,  Larisa NOVAKOVSKY ,  Mark SCHMISSEUR ,  Eric RASMUSSEN ,  Stephen VAN DOREN ,  Yen-Cheng LIU

发明人： Wei CHEN ,  Eswaramoorthi NALLUSAMY ,  Larisa NOVAKOVSKY ,  Mark SCHMISSEUR ,  Eric RASMUSSEN ,  Stephen VAN DOREN ,  Yen-Cheng LIU

IPC分类号： G06F12/0891 ,  G06F12/02 ,  G06F12/0802

摘要： Techniques and mechanisms for capturing an image of processor state at one node of multiple nodes of a multi-processor platform, where the processor state includes some version of data which the node retrieved from another node of the platform. In an embodiment, a disruption of power is detected when a processor of a first node has a cached version of data which was retrieved from a second node. In response to detection of the disruption, the data is saved to a system memory of the first node as part of an image of the processor's state. The image further comprises address information, corresponding to the data, which indicates a memory location at the second node. In another embodiment, processor state is restored during a boot-up of the node, wherein the state includes the captured version of data which was previously retrieved from the second node.

公开(公告)号：US20170017286A1

公开(公告)日：2017-01-19

申请号：US15281587

申请日：2016-09-30

申请人： YEN-CHENG LIU ,  P. KEONG OR ,  KRISHNAKANTH V. SISTLA ,  GANAPATI SRINIVASA

发明人： YEN-CHENG LIU ,  P. KEONG OR ,  KRISHNAKANTH V. SISTLA ,  GANAPATI SRINIVASA

IPC分类号： G06F1/32 ,  G06F15/80 ,  G06F1/20

CPC分类号： G06F1/3243 ,  G06F1/206 ,  G06F1/3203 ,  G06F1/3206 ,  G06F1/324 ,  G06F1/3275 ,  G06F1/3287 ,  G06F12/0811 ,  G06F15/80 ,  G06F2212/283 ,  G11C7/1072 ,  G11C7/1075 ,  Y02D10/16

摘要： A method and apparatus to monitor architecture events is disclosed. The architecture events are linked together via a push bus mechanism with each architectural event having a designated time slot. There is at least one branch of the push bus in each core. Each branch of the push bus may monitor one core with all the architectural events. All the data collected from the events by the push bus is then sent to a power control unit.

公开(公告)号：US20120089850A1

公开(公告)日：2012-04-12

申请号：US13329700

申请日：2011-12-19

申请人： Yen-Cheng Liu ,  P. Keong Or ,  Krishnakanth Sistla ,  Ganapati Srinivasa

发明人： Yen-Cheng Liu ,  P. Keong Or ,  Krishnakanth Sistla ,  Ganapati Srinivasa

IPC分类号： G06F1/26

CPC分类号： G06F1/3243 ,  G06F1/206 ,  G06F1/3203 ,  G06F1/3206 ,  G06F1/324 ,  G06F1/3275 ,  G06F1/3287 ,  G06F12/0811 ,  G06F15/80 ,  G06F2212/283 ,  G11C7/1072 ,  G11C7/1075 ,  Y02D10/16

摘要： A method and apparatus to monitor architecture events is disclosed. The architecture events are linked together via a push bus mechanism with each architectural event having a designated time slot. There is at least one branch of the push bus in each core. Each branch of the push bus may monitor one core with all the architectural events. All the data collected from the events by the push bus is then sent to a power control unit.

摘要翻译： 公开了一种监视架构事件的方法和装置。 架构事件通过推送总线机制链接在一起，每个架构事件都具有指定的时隙。 在每个核心中至少有一个分支的推送总线。 推送总线的每个分支可以监视一个核心与所有的架构事件。 然后将通过推送总线从事件收集的所有数据发送到电源控制单元。

公开(公告)号：US20120079032A1

公开(公告)日：2012-03-29

申请号：US12889802

申请日：2010-09-24

申请人： James R. Vash ,  Vida Vakilotojar ,  Bongjin Jung ,  Yen-Cheng Liu

发明人： James R. Vash ,  Vida Vakilotojar ,  Bongjin Jung ,  Yen-Cheng Liu

IPC分类号： G06F15/16 ,  G06F5/00 ,  G06F12/08

CPC分类号： H04L67/10 ,  G06F15/17325

摘要： Methods, apparatus and systems for facilitating one-way ordering of otherwise independent message classes. A one-way message ordering mechanism facilitates one-way ordering of messages of different message classes sent between interconnects employing independent pathways for the message classes. In one aspect, messages of a second message class may not pass messages of a first message class. Moreover, when messages of the first and second classes are received in sequence, the ordering mechanism ensures that messages of the first class are forwarded to, and received at, a next hop prior to forwarding messages of the second class.

摘要翻译： 用于促进独立消息类别的单向排序的方法，装置和系统。 单向消息排序机制有助于在使用消息类的独立路径的互连之间发送的不同消息类别的消息的单向排序。 在一个方面，第二消息类的消息可能不会传递第一消息类的消息。 此外，当顺序地接收到第一类和第二类的消息时，排序机制确保在转发第二类的消息之前将第一类的消息转发到下一跳并在其中接收。

公开(公告)号：US08117478B2

公开(公告)日：2012-02-14

申请号：US11618477

申请日：2006-12-29

申请人： Yen-Cheng Liu ,  P Keong Or ,  Krishnakanth Sistia ,  Ganapati Srinivasa

发明人： Yen-Cheng Liu ,  P Keong Or ,  Krishnakanth Sistia ,  Ganapati Srinivasa

IPC分类号： G06F1/00

CPC分类号： G06F1/3243 ,  G06F1/206 ,  G06F1/3203 ,  G06F1/3206 ,  G06F1/324 ,  G06F1/3275 ,  G06F1/3287 ,  G06F12/0811 ,  G06F15/80 ,  G06F2212/283 ,  G11C7/1072 ,  G11C7/1075 ,  Y02D10/16

摘要： A method and apparatus to monitor architecture events is disclosed. The architecture events are linked together via a push bus mechanism with each architectural event having a designated time slot. There is at least one branch of the push bus in each core. Each branch of the push bus may monitor one core with all the architectural events. All the data collected from the events by the push bus is then sent to a power control unit.

摘要翻译： 公开了一种监视架构事件的方法和装置。 架构事件通过推送总线机制链接在一起，每个架构事件具有指定的时隙。 在每个核心中至少有一个分支的推送总线。 推送总线的每个分支可以监视一个核心与所有的架构事件。 然后将通过推送总线从事件收集的所有数据发送到电源控制单元。

公开(公告)号：US07689778B2

公开(公告)日：2010-03-30

申请号：US11000768

申请日：2004-11-30

申请人： Yen-Cheng Liu ,  Krishnakanth V. Sistla ,  George Cai ,  Jeffrey D. Gilbert

发明人： Yen-Cheng Liu ,  Krishnakanth V. Sistla ,  George Cai ,  Jeffrey D. Gilbert

IPC分类号： G06F13/00

CPC分类号： G06F12/0831

摘要： In various embodiments, hardware, software and firmware or combinations thereof may be used to prevent cache conflicts within microprocessors and/or computer systems. More particularly, embodiments of the invention relate to a technique to prevent cache conflicts within a processor and/or computer system in which a number of accesses may be made to a particular cache or group of caches.

摘要翻译： 在各种实施例中，可以使用硬件，软件和固件或其组合来防止微处理器和/或计算机系统内的高速缓存冲突。 更具体地，本发明的实施例涉及一种防止处理器和/或计算机系统内的高速缓存冲突的技术，其中可以对特定高速缓存或一组高速缓存进行多次访问。

公开(公告)号：US20080002603A1

公开(公告)日：2008-01-03

申请号：US11479009

申请日：2006-06-29

申请人： Steven R. Hutsell ,  Krishnakanth Sistla ,  Yen-cheng Liu

发明人： Steven R. Hutsell ,  Krishnakanth Sistla ,  Yen-cheng Liu

IPC分类号： H04B7/185

CPC分类号： G06F1/3203 ,  G06F1/3287 ,  Y02D10/171

摘要： A system and method to provide source controlled dynamic power management. An activity detector in a source determines expected future resource usage. Based on that expected usage, the source generates a power management command and sends that command to a destination. The destination then adjusts the power level of the resource based in the command.

摘要翻译： 一种提供源控制动态电源管理的系统和方法。 源中的活动检测器确定将来的资源使用量。 根据该预期用途，源产生电源管理命令并将该命令发送到目的地。 然后，目标将根据命令调整资源的功率级别。

公开(公告)号：US20060117148A1

公开(公告)日：2006-06-01

申请号：US11000768

申请日：2004-11-30

申请人： Yen-Cheng Liu ,  Krishnakanth Sistla ,  George Cai ,  Jeffrey Gilbert

发明人： Yen-Cheng Liu ,  Krishnakanth Sistla ,  George Cai ,  Jeffrey Gilbert

IPC分类号： G06F12/00

CPC分类号： G06F12/0831

摘要： Preventing cache conflicts within microprocessors and/or computer systems. More particularly, embodiments of the invention relate to a technique to prevent cache conflicts within a processor and/or computer system in which a number of accesses may be made to a particular cache or group of caches.

摘要翻译： 防止微处理器和/或计算机系统中的缓存冲突。 更具体地，本发明的实施例涉及一种防止处理器和/或计算机系统内的高速缓存冲突的技术，其中可以对特定高速缓存或一组高速缓存进行多次访问。

公开(公告)号：US20200311018A1

公开(公告)日：2020-10-01

申请号：US16364619

申请日：2019-03-26

申请人： Tejpal Singh ,  Yedidya Hilewitz ,  Ankush Varma ,  Yen-Cheng Liu ,  Krishnakanth V. Sistla ,  Jeffrey Chamberlain

发明人： Tejpal Singh ,  Yedidya Hilewitz ,  Ankush Varma ,  Yen-Cheng Liu ,  Krishnakanth V. Sistla ,  Jeffrey Chamberlain

IPC分类号： G06F15/78 ,  G06F9/54 ,  G06F1/3234 ,  G06F1/3296 ,  G06F9/30

摘要： In one embodiment, an apparatus includes an interconnect to couple a plurality of processing circuits. The interconnect may include a pipe stage circuit coupled between a first processing circuit and a second processing circuit. This pipe stage circuit may include: a pipe stage component having a first input to receive a signal via the interconnect and a first output to output the signal; and a selection circuit having a first input to receive the signal from the first output of the pipe stage component and a second input to receive the signal via a bypass path, where the selection circuit is dynamically controllable to output the signal received from the first output of the pipe stage component or the signal received via the bypass path. Other embodiments are described and claimed.